1 | //===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the TableGen definitions from which the ARM FP16 header |
10 | // file will be generated. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | include "arm_neon_incl.td" |
15 | |
16 | // ARMv8.2-A FP16 intrinsics. |
17 | let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarch64__)" in { |
18 | |
19 | // Negate |
20 | def VNEGSH : SInst<"vneg", "ss", "Sh">; |
21 | |
22 | // Reciprocal/Sqrt |
23 | def SCALAR_FRECPSH : IInst<"vrecps", "sss", "Sh">; |
24 | def FSQRTSH : SInst<"vsqrt", "ss", "Sh">; |
25 | def SCALAR_FRSQRTSH : IInst<"vrsqrts", "sss", "Sh">; |
26 | |
27 | // Reciprocal Estimate |
28 | def SCALAR_FRECPEH : IInst<"vrecpe", "ss", "Sh">; |
29 | |
30 | // Reciprocal Exponent |
31 | def SCALAR_FRECPXH : IInst<"vrecpx", "ss", "Sh">; |
32 | |
33 | // Reciprocal Square Root Estimate |
34 | def SCALAR_FRSQRTEH : IInst<"vrsqrte", "ss", "Sh">; |
35 | |
36 | // Rounding |
37 | def FRINTZ_S64H : SInst<"vrnd", "ss", "Sh">; |
38 | def FRINTA_S64H : SInst<"vrnda", "ss", "Sh">; |
39 | def FRINTI_S64H : SInst<"vrndi", "ss", "Sh">; |
40 | def FRINTM_S64H : SInst<"vrndm", "ss", "Sh">; |
41 | def FRINTN_S64H : SInst<"vrndn", "ss", "Sh">; |
42 | def FRINTP_S64H : SInst<"vrndp", "ss", "Sh">; |
43 | def FRINTX_S64H : SInst<"vrndx", "ss", "Sh">; |
44 | |
45 | // Conversion |
46 | def SCALAR_SCVTFSH : SInst<"vcvth_f16", "Ys", "silUsUiUl">; |
47 | def SCALAR_FCVTZSH : SInst<"vcvt_s16", "$s", "Sh">; |
48 | def SCALAR_FCVTZSH1 : SInst<"vcvt_s32", "Is", "Sh">; |
49 | def SCALAR_FCVTZSH2 : SInst<"vcvt_s64", "Ls", "Sh">; |
50 | def SCALAR_FCVTZUH : SInst<"vcvt_u16", "bs", "Sh">; |
51 | def SCALAR_FCVTZUH1 : SInst<"vcvt_u32", "Us", "Sh">; |
52 | def SCALAR_FCVTZUH2 : SInst<"vcvt_u64", "Os", "Sh">; |
53 | def SCALAR_FCVTASH : SInst<"vcvta_s16", "$s", "Sh">; |
54 | def SCALAR_FCVTASH1 : SInst<"vcvta_s32", "Is", "Sh">; |
55 | def SCALAR_FCVTASH2 : SInst<"vcvta_s64", "Ls", "Sh">; |
56 | def SCALAR_FCVTAUH : SInst<"vcvta_u16", "bs", "Sh">; |
57 | def SCALAR_FCVTAUH1 : SInst<"vcvta_u32", "Us", "Sh">; |
58 | def SCALAR_FCVTAUH2 : SInst<"vcvta_u64", "Os", "Sh">; |
59 | def SCALAR_FCVTMSH : SInst<"vcvtm_s16", "$s", "Sh">; |
60 | def SCALAR_FCVTMSH1 : SInst<"vcvtm_s32", "Is", "Sh">; |
61 | def SCALAR_FCVTMSH2 : SInst<"vcvtm_s64", "Ls", "Sh">; |
62 | def SCALAR_FCVTMUH : SInst<"vcvtm_u16", "bs", "Sh">; |
63 | def SCALAR_FCVTMUH1 : SInst<"vcvtm_u32", "Us", "Sh">; |
64 | def SCALAR_FCVTMUH2 : SInst<"vcvtm_u64", "Os", "Sh">; |
65 | def SCALAR_FCVTNSH : SInst<"vcvtn_s16", "$s", "Sh">; |
66 | def SCALAR_FCVTNSH1 : SInst<"vcvtn_s32", "Is", "Sh">; |
67 | def SCALAR_FCVTNSH2 : SInst<"vcvtn_s64", "Ls", "Sh">; |
68 | def SCALAR_FCVTNUH : SInst<"vcvtn_u16", "bs", "Sh">; |
69 | def SCALAR_FCVTNUH1 : SInst<"vcvtn_u32", "Us", "Sh">; |
70 | def SCALAR_FCVTNUH2 : SInst<"vcvtn_u64", "Os", "Sh">; |
71 | def SCALAR_FCVTPSH : SInst<"vcvtp_s16", "$s", "Sh">; |
72 | def SCALAR_FCVTPSH1 : SInst<"vcvtp_s32", "Is", "Sh">; |
73 | def SCALAR_FCVTPSH2 : SInst<"vcvtp_s64", "Ls", "Sh">; |
74 | def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "bs", "Sh">; |
75 | def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "Us", "Sh">; |
76 | def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "Os", "Sh">; |
77 | let isVCVT_N = 1 in { |
78 | def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">; |
79 | def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">; |
80 | def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">; |
81 | def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">; |
82 | def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">; |
83 | def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">; |
84 | def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">; |
85 | } |
86 | // Comparison |
87 | def SCALAR_CMEQRH : SInst<"vceq", "bss", "Sh">; |
88 | def SCALAR_CMEQZH : SInst<"vceqz", "bs", "Sh">; |
89 | def SCALAR_CMGERH : SInst<"vcge", "bss", "Sh">; |
90 | def SCALAR_CMGEZH : SInst<"vcgez", "bs", "Sh">; |
91 | def SCALAR_CMGTRH : SInst<"vcgt", "bss", "Sh">; |
92 | def SCALAR_CMGTZH : SInst<"vcgtz", "bs", "Sh">; |
93 | def SCALAR_CMLERH : SInst<"vcle", "bss", "Sh">; |
94 | def SCALAR_CMLEZH : SInst<"vclez", "bs", "Sh">; |
95 | def SCALAR_CMLTH : SInst<"vclt", "bss", "Sh">; |
96 | def SCALAR_CMLTZH : SInst<"vcltz", "bs", "Sh">; |
97 | |
98 | // Absolute Compare Mask Greater Than Or Equal |
99 | def SCALAR_FACGEH : IInst<"vcage", "bss", "Sh">; |
100 | def SCALAR_FACLEH : IInst<"vcale", "bss", "Sh">; |
101 | |
102 | // Absolute Compare Mask Greater Than |
103 | def SCALAR_FACGT : IInst<"vcagt", "bss", "Sh">; |
104 | def SCALAR_FACLT : IInst<"vcalt", "bss", "Sh">; |
105 | |
106 | // Scalar Absolute Value |
107 | def SCALAR_ABSH : SInst<"vabs", "ss", "Sh">; |
108 | |
109 | // Scalar Absolute Difference |
110 | def SCALAR_ABDH: IInst<"vabd", "sss", "Sh">; |
111 | |
112 | // Add/Sub |
113 | def VADDSH : SInst<"vadd", "sss", "Sh">; |
114 | def VSUBHS : SInst<"vsub", "sss", "Sh">; |
115 | |
116 | // Max/Min |
117 | def VMAXHS : SInst<"vmax", "sss", "Sh">; |
118 | def VMINHS : SInst<"vmin", "sss", "Sh">; |
119 | def FMAXNMHS : SInst<"vmaxnm", "sss", "Sh">; |
120 | def FMINNMHS : SInst<"vminnm", "sss", "Sh">; |
121 | |
122 | // Multiplication/Division |
123 | def VMULHS : SInst<"vmul", "sss", "Sh">; |
124 | def MULXHS : SInst<"vmulx", "sss", "Sh">; |
125 | def FDIVHS : SInst<"vdiv", "sss", "Sh">; |
126 | |
127 | // Vector fused multiply-add operations |
128 | def VFMAHS : SInst<"vfma", "ssss", "Sh">; |
129 | def VFMSHS : SInst<"vfms", "ssss", "Sh">; |
130 | } |
131 | |