| 1 | // REQUIRES: arm-registered-target |
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| 2 | // RUN: %clang_cc1 -triple armv7 -target-feature +neon %s -emit-llvm -o /dev/null |
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| 3 | |
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| 4 | char bar(); |
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| 5 | |
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| 6 | void t1(int x, char y) { |
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| 7 | __asm__ volatile("mcr p15, 0, %1, c9, c12, 5;" |
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| 8 | "mrc p15, 0, %0, c9, c13, 2;" |
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| 9 | : "=r" (x) |
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| 10 | : "r" (bar())); // no warning |
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| 11 | __asm__ volatile("foo %0, %1" |
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| 12 | : "+r" (x), |
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| 13 | "+r" (y) |
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| 14 | :); |
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| 15 | __asm__ volatile("ldrb %0, [%1]" : "=r" (y) : "r" (x)); // no warning |
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| 16 | } |
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| 17 | |
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| 18 | // <rdar://problem/12284092> |
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| 19 | typedef __attribute__((neon_vector_type(2))) long long int64x2_t; |
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| 20 | typedef struct int64x2x4_t { |
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| 21 | int64x2_t val[4]; |
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| 22 | } int64x2x4_t; |
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| 23 | int64x2x4_t t2(const long long a[]) { |
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| 24 | int64x2x4_t r; |
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| 25 | __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }" |
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| 26 | : [r0] "=r"(r.val[0]), // expected-warning {{value size does not match register size specified by the constraint and modifier}} |
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| 27 | [r1] "=r"(r.val[1]), // expected-warning {{value size does not match register size specified by the constraint and modifier}} |
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| 28 | [r2] "=r"(r.val[2]), // expected-warning {{value size does not match register size specified by the constraint and modifier}} |
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| 29 | [r3] "=r"(r.val[3]) // expected-warning {{value size does not match register size specified by the constraint and modifier}} |
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| 30 | : [a] "r"(a)); |
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| 31 | return r; |
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| 32 | } |
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| 33 | |
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