| 1 | // RUN: %clang_cc1 %s -emit-llvm -o - -triple=arm64-apple-ios7 | FileCheck %s |
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| 2 | |
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| 3 | // Memory ordering values. |
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| 4 | enum { |
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| 5 | memory_order_relaxed = 0, |
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| 6 | memory_order_consume = 1, |
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| 7 | memory_order_acquire = 2, |
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| 8 | memory_order_release = 3, |
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| 9 | memory_order_acq_rel = 4, |
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| 10 | memory_order_seq_cst = 5 |
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| 11 | }; |
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| 12 | |
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| 13 | typedef struct { void *a, *b; } pointer_pair_t; |
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| 14 | typedef struct { void *a, *b, *c, *d; } pointer_quad_t; |
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| 15 | |
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| 16 | // rdar://13489679 |
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| 17 | |
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| 18 | extern _Atomic(_Bool) a_bool; |
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| 19 | extern _Atomic(float) a_float; |
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| 20 | extern _Atomic(void*) a_pointer; |
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| 21 | extern _Atomic(pointer_pair_t) a_pointer_pair; |
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| 22 | extern _Atomic(pointer_quad_t) a_pointer_quad; |
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| 23 | |
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| 24 | // CHECK-LABEL:define void @test0() |
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| 25 | // CHECK: [[TEMP:%.*]] = alloca i8, align 1 |
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| 26 | // CHECK-NEXT: store i8 1, i8* [[TEMP]] |
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| 27 | // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[TEMP]], align 1 |
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| 28 | // CHECK-NEXT: store atomic i8 [[T0]], i8* @a_bool seq_cst, align 1 |
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| 29 | void test0() { |
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| 30 | __c11_atomic_store(&a_bool, 1, memory_order_seq_cst); |
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| 31 | } |
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| 32 | |
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| 33 | // CHECK-LABEL:define void @test1() |
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| 34 | // CHECK: [[TEMP:%.*]] = alloca float, align 4 |
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| 35 | // CHECK-NEXT: store float 3.000000e+00, float* [[TEMP]] |
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| 36 | // CHECK-NEXT: [[T0:%.*]] = bitcast float* [[TEMP]] to i32* |
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| 37 | // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[T0]], align 4 |
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| 38 | // CHECK-NEXT: store atomic i32 [[T1]], i32* bitcast (float* @a_float to i32*) seq_cst, align 4 |
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| 39 | void test1() { |
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| 40 | __c11_atomic_store(&a_float, 3, memory_order_seq_cst); |
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| 41 | } |
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| 42 | |
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| 43 | // CHECK-LABEL:define void @test2() |
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| 44 | // CHECK: [[TEMP:%.*]] = alloca i8*, align 8 |
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| 45 | // CHECK-NEXT: store i8* @a_bool, i8** [[TEMP]] |
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| 46 | // CHECK-NEXT: [[T0:%.*]] = bitcast i8** [[TEMP]] to i64* |
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| 47 | // CHECK-NEXT: [[T1:%.*]] = load i64, i64* [[T0]], align 8 |
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| 48 | // CHECK-NEXT: store atomic i64 [[T1]], i64* bitcast (i8** @a_pointer to i64*) seq_cst, align 8 |
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| 49 | void test2() { |
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| 50 | __c11_atomic_store(&a_pointer, &a_bool, memory_order_seq_cst); |
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| 51 | } |
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| 52 | |
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| 53 | // CHECK-LABEL:define void @test3( |
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| 54 | // CHECK: [[PAIR:%.*]] = alloca [[PAIR_T:%.*]], align 8 |
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| 55 | // CHECK-NEXT: [[TEMP:%.*]] = alloca [[PAIR_T]], align 8 |
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| 56 | // CHECK: llvm.memcpy |
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| 57 | // CHECK-NEXT: [[T0:%.*]] = bitcast [[PAIR_T]]* [[TEMP]] to i128* |
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| 58 | // CHECK-NEXT: [[T1:%.*]] = load i128, i128* [[T0]], align 8 |
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| 59 | // CHECK-NEXT: store atomic i128 [[T1]], i128* bitcast ([[PAIR_T]]* @a_pointer_pair to i128*) seq_cst, align 16 |
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| 60 | void test3(pointer_pair_t pair) { |
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| 61 | __c11_atomic_store(&a_pointer_pair, pair, memory_order_seq_cst); |
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| 62 | } |
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| 63 | |
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| 64 | // CHECK-LABEL:define void @test4( |
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| 65 | // CHECK: [[TEMP:%.*]] = alloca [[QUAD_T:%.*]], align 8 |
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| 66 | // CHECK-NEXT: [[T0:%.*]] = bitcast [[QUAD_T]]* [[TEMP]] to i8* |
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| 67 | // CHECK-NEXT: [[T1:%.*]] = bitcast [[QUAD_T]]* {{%.*}} to i8* |
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| 68 | // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[T0]], i8* align 8 [[T1]], i64 32, i1 false) |
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| 69 | // CHECK-NEXT: [[T0:%.*]] = bitcast [[QUAD_T]]* [[TEMP]] to i256* |
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| 70 | // CHECK-NEXT: [[T1:%.*]] = bitcast i256* [[T0]] to i8* |
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| 71 | // CHECK-NEXT: call void @__atomic_store(i64 32, i8* bitcast ([[QUAD_T]]* @a_pointer_quad to i8*), i8* [[T1]], i32 5) |
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| 72 | void test4(pointer_quad_t quad) { |
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| 73 | __c11_atomic_store(&a_pointer_quad, quad, memory_order_seq_cst); |
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| 74 | } |
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| 75 | |
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