| 1 | // RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +bmi -emit-llvm -o - -Wall -Werror | FileCheck %s |
| 2 | |
| 3 | |
| 4 | #include <immintrin.h> |
| 5 | |
| 6 | // NOTE: This should match the tests in llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll |
| 7 | |
| 8 | // The double underscore intrinsics are for compatibility with |
| 9 | // AMD's BMI interface. The single underscore intrinsics |
| 10 | // are for compatibility with Intel's BMI interface. |
| 11 | // Apart from the underscores, the interfaces are identical |
| 12 | // except in one case: although the 'bextr' register-form |
| 13 | // instruction is identical in hardware, the AMD and Intel |
| 14 | // intrinsics are different! |
| 15 | |
| 16 | unsigned short test__tzcnt_u16(unsigned short __X) { |
| 17 | // CHECK-LABEL: test__tzcnt_u16 |
| 18 | // CHECK: i16 @llvm.cttz.i16(i16 %{{.*}}, i1 false) |
| 19 | return __tzcnt_u16(__X); |
| 20 | } |
| 21 | |
| 22 | unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) { |
| 23 | // CHECK-LABEL: test__andn_u32 |
| 24 | // CHECK: xor i32 %{{.*}}, -1 |
| 25 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 26 | return __andn_u32(__X, __Y); |
| 27 | } |
| 28 | |
| 29 | unsigned int test__bextr_u32(unsigned int __X, unsigned int __Y) { |
| 30 | // CHECK-LABEL: test__bextr_u32 |
| 31 | // CHECK: i32 @llvm.x86.bmi.bextr.32(i32 %{{.*}}, i32 %{{.*}}) |
| 32 | return __bextr_u32(__X, __Y); |
| 33 | } |
| 34 | |
| 35 | unsigned int test__blsi_u32(unsigned int __X) { |
| 36 | // CHECK-LABEL: test__blsi_u32 |
| 37 | // CHECK: sub i32 0, %{{.*}} |
| 38 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 39 | return __blsi_u32(__X); |
| 40 | } |
| 41 | |
| 42 | unsigned int test__blsmsk_u32(unsigned int __X) { |
| 43 | // CHECK-LABEL: test__blsmsk_u32 |
| 44 | // CHECK: sub i32 %{{.*}}, 1 |
| 45 | // CHECK: xor i32 %{{.*}}, %{{.*}} |
| 46 | return __blsmsk_u32(__X); |
| 47 | } |
| 48 | |
| 49 | unsigned int test__blsr_u32(unsigned int __X) { |
| 50 | // CHECK-LABEL: test__blsr_u32 |
| 51 | // CHECK: sub i32 %{{.*}}, 1 |
| 52 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 53 | return __blsr_u32(__X); |
| 54 | } |
| 55 | |
| 56 | unsigned int test__tzcnt_u32(unsigned int __X) { |
| 57 | // CHECK-LABEL: test__tzcnt_u32 |
| 58 | // CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false) |
| 59 | return __tzcnt_u32(__X); |
| 60 | } |
| 61 | |
| 62 | int test_mm_tzcnt_32(unsigned int __X) { |
| 63 | // CHECK-LABEL: test_mm_tzcnt_32 |
| 64 | // CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false) |
| 65 | return _mm_tzcnt_32(__X); |
| 66 | } |
| 67 | |
| 68 | unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) { |
| 69 | // CHECK-LABEL: test__andn_u64 |
| 70 | // CHECK: xor i64 %{{.*}}, -1 |
| 71 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 72 | return __andn_u64(__X, __Y); |
| 73 | } |
| 74 | |
| 75 | unsigned long long test__bextr_u64(unsigned long __X, unsigned long __Y) { |
| 76 | // CHECK-LABEL: test__bextr_u64 |
| 77 | // CHECK: i64 @llvm.x86.bmi.bextr.64(i64 %{{.*}}, i64 %{{.*}}) |
| 78 | return __bextr_u64(__X, __Y); |
| 79 | } |
| 80 | |
| 81 | unsigned long long test__blsi_u64(unsigned long long __X) { |
| 82 | // CHECK-LABEL: test__blsi_u64 |
| 83 | // CHECK: sub i64 0, %{{.*}} |
| 84 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 85 | return __blsi_u64(__X); |
| 86 | } |
| 87 | |
| 88 | unsigned long long test__blsmsk_u64(unsigned long long __X) { |
| 89 | // CHECK-LABEL: test__blsmsk_u64 |
| 90 | // CHECK: sub i64 %{{.*}}, 1 |
| 91 | // CHECK: xor i64 %{{.*}}, %{{.*}} |
| 92 | return __blsmsk_u64(__X); |
| 93 | } |
| 94 | |
| 95 | unsigned long long test__blsr_u64(unsigned long long __X) { |
| 96 | // CHECK-LABEL: test__blsr_u64 |
| 97 | // CHECK: sub i64 %{{.*}}, 1 |
| 98 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 99 | return __blsr_u64(__X); |
| 100 | } |
| 101 | |
| 102 | unsigned long long test__tzcnt_u64(unsigned long long __X) { |
| 103 | // CHECK-LABEL: test__tzcnt_u64 |
| 104 | // CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false) |
| 105 | return __tzcnt_u64(__X); |
| 106 | } |
| 107 | |
| 108 | long long test_mm_tzcnt_64(unsigned long long __X) { |
| 109 | // CHECK-LABEL: test_mm_tzcnt_64 |
| 110 | // CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false) |
| 111 | return _mm_tzcnt_64(__X); |
| 112 | } |
| 113 | |
| 114 | // Intel intrinsics |
| 115 | |
| 116 | unsigned short test_tzcnt_u16(unsigned short __X) { |
| 117 | // CHECK-LABEL: test_tzcnt_u16 |
| 118 | // CHECK: i16 @llvm.cttz.i16(i16 %{{.*}}, i1 false) |
| 119 | return _tzcnt_u16(__X); |
| 120 | } |
| 121 | |
| 122 | unsigned int test_andn_u32(unsigned int __X, unsigned int __Y) { |
| 123 | // CHECK-LABEL: test_andn_u32 |
| 124 | // CHECK: xor i32 %{{.*}}, -1 |
| 125 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 126 | return _andn_u32(__X, __Y); |
| 127 | } |
| 128 | |
| 129 | unsigned int test_bextr_u32(unsigned int __X, unsigned int __Y, |
| 130 | unsigned int __Z) { |
| 131 | // CHECK-LABEL: test_bextr_u32 |
| 132 | // CHECK: and i32 %{{.*}}, 255 |
| 133 | // CHECK: and i32 %{{.*}}, 255 |
| 134 | // CHECK: shl i32 %{{.*}}, 8 |
| 135 | // CHECK: or i32 %{{.*}}, %{{.*}} |
| 136 | // CHECK: i32 @llvm.x86.bmi.bextr.32(i32 %{{.*}}, i32 %{{.*}}) |
| 137 | return _bextr_u32(__X, __Y, __Z); |
| 138 | } |
| 139 | |
| 140 | unsigned int test_blsi_u32(unsigned int __X) { |
| 141 | // CHECK-LABEL: test_blsi_u32 |
| 142 | // CHECK: sub i32 0, %{{.*}} |
| 143 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 144 | return _blsi_u32(__X); |
| 145 | } |
| 146 | |
| 147 | unsigned int test_blsmsk_u32(unsigned int __X) { |
| 148 | // CHECK-LABEL: test_blsmsk_u32 |
| 149 | // CHECK: sub i32 %{{.*}}, 1 |
| 150 | // CHECK: xor i32 %{{.*}}, %{{.*}} |
| 151 | return _blsmsk_u32(__X); |
| 152 | } |
| 153 | |
| 154 | unsigned int test_blsr_u32(unsigned int __X) { |
| 155 | // CHECK-LABEL: test_blsr_u32 |
| 156 | // CHECK: sub i32 %{{.*}}, 1 |
| 157 | // CHECK: and i32 %{{.*}}, %{{.*}} |
| 158 | return _blsr_u32(__X); |
| 159 | } |
| 160 | |
| 161 | unsigned int test_tzcnt_u32(unsigned int __X) { |
| 162 | // CHECK-LABEL: test_tzcnt_u32 |
| 163 | // CHECK: i32 @llvm.cttz.i32(i32 %{{.*}}, i1 false) |
| 164 | return _tzcnt_u32(__X); |
| 165 | } |
| 166 | |
| 167 | unsigned long long test_andn_u64(unsigned long __X, unsigned long __Y) { |
| 168 | // CHECK-LABEL: test_andn_u64 |
| 169 | // CHECK: xor i64 %{{.*}}, -1 |
| 170 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 171 | return _andn_u64(__X, __Y); |
| 172 | } |
| 173 | |
| 174 | unsigned long long test_bextr_u64(unsigned long __X, unsigned int __Y, |
| 175 | unsigned int __Z) { |
| 176 | // CHECK-LABEL: test_bextr_u64 |
| 177 | // CHECK: and i32 %{{.*}}, 255 |
| 178 | // CHECK: and i32 %{{.*}}, 255 |
| 179 | // CHECK: shl i32 %{{.*}}, 8 |
| 180 | // CHECK: or i32 %{{.*}}, %{{.*}} |
| 181 | // CHECK: zext i32 %{{.*}} to i64 |
| 182 | // CHECK: i64 @llvm.x86.bmi.bextr.64(i64 %{{.*}}, i64 %{{.*}}) |
| 183 | return _bextr_u64(__X, __Y, __Z); |
| 184 | } |
| 185 | |
| 186 | unsigned long long test_blsi_u64(unsigned long long __X) { |
| 187 | // CHECK-LABEL: test_blsi_u64 |
| 188 | // CHECK: sub i64 0, %{{.*}} |
| 189 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 190 | return _blsi_u64(__X); |
| 191 | } |
| 192 | |
| 193 | unsigned long long test_blsmsk_u64(unsigned long long __X) { |
| 194 | // CHECK-LABEL: test_blsmsk_u64 |
| 195 | // CHECK: sub i64 %{{.*}}, 1 |
| 196 | // CHECK: xor i64 %{{.*}}, %{{.*}} |
| 197 | return _blsmsk_u64(__X); |
| 198 | } |
| 199 | |
| 200 | unsigned long long test_blsr_u64(unsigned long long __X) { |
| 201 | // CHECK-LABEL: test_blsr_u64 |
| 202 | // CHECK: sub i64 %{{.*}}, 1 |
| 203 | // CHECK: and i64 %{{.*}}, %{{.*}} |
| 204 | return _blsr_u64(__X); |
| 205 | } |
| 206 | |
| 207 | unsigned long long test_tzcnt_u64(unsigned long long __X) { |
| 208 | // CHECK-LABEL: test_tzcnt_u64 |
| 209 | // CHECK: i64 @llvm.cttz.i64(i64 %{{.*}}, i1 false) |
| 210 | return _tzcnt_u64(__X); |
| 211 | } |
| 212 | |