| 1 | // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \ |
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| 2 | // RUN: -target-feature +crypto -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s |
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| 3 | |
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| 4 | // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ |
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| 5 | // RUN: -target-feature +crypto -emit-llvm -O1 -o - %s | FileCheck %s |
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| 6 | // RUN: not %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ |
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| 7 | // RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s |
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| 8 | |
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| 9 | // Test new aarch64 intrinsics and types |
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| 10 | |
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| 11 | #include <arm_neon.h> |
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| 12 | |
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| 13 | uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) { |
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| 14 | // CHECK-LABEL: @test_vaeseq_u8 |
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| 15 | // CHECK-NO-CRYPTO: warning: implicit declaration of function 'vaeseq_u8' is invalid in C99 |
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| 16 | return vaeseq_u8(data, key); |
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| 17 | // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aese(<16 x i8> %data, <16 x i8> %key) |
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| 18 | } |
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| 19 | |
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| 20 | uint8x16_t test_vaesdq_u8(uint8x16_t data, uint8x16_t key) { |
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| 21 | // CHECK-LABEL: @test_vaesdq_u8 |
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| 22 | return vaesdq_u8(data, key); |
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| 23 | // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesd(<16 x i8> %data, <16 x i8> %key) |
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| 24 | } |
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| 25 | |
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| 26 | uint8x16_t test_vaesmcq_u8(uint8x16_t data) { |
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| 27 | // CHECK-LABEL: @test_vaesmcq_u8 |
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| 28 | return vaesmcq_u8(data); |
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| 29 | // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesmc(<16 x i8> %data) |
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| 30 | } |
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| 31 | |
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| 32 | uint8x16_t test_vaesimcq_u8(uint8x16_t data) { |
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| 33 | // CHECK-LABEL: @test_vaesimcq_u8 |
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| 34 | return vaesimcq_u8(data); |
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| 35 | // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesimc(<16 x i8> %data) |
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| 36 | } |
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| 37 | |
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| 38 | uint32_t test_vsha1h_u32(uint32_t hash_e) { |
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| 39 | // CHECK-LABEL: @test_vsha1h_u32 |
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| 40 | return vsha1h_u32(hash_e); |
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| 41 | // CHECK: call i32 @llvm.{{arm.neon|aarch64.crypto}}.sha1h(i32 %hash_e) |
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| 42 | } |
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| 43 | |
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| 44 | uint32x4_t test_vsha1su1q_u32(uint32x4_t w0_3, uint32x4_t w12_15) { |
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| 45 | // CHECK-LABEL: @test_vsha1su1q_u32 |
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| 46 | return vsha1su1q_u32(w0_3, w12_15); |
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| 47 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su1(<4 x i32> %w0_3, <4 x i32> %w12_15) |
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| 48 | } |
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| 49 | |
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| 50 | uint32x4_t test_vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7) { |
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| 51 | // CHECK-LABEL: @test_vsha256su0q_u32 |
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| 52 | return vsha256su0q_u32(w0_3, w4_7); |
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| 53 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) |
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| 54 | } |
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| 55 | |
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| 56 | uint32x4_t test_vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) { |
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| 57 | // CHECK-LABEL: @test_vsha1cq_u32 |
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| 58 | return vsha1cq_u32(hash_abcd, hash_e, wk); |
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| 59 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) |
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| 60 | } |
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| 61 | |
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| 62 | uint32x4_t test_vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) { |
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| 63 | // CHECK-LABEL: @test_vsha1pq_u32 |
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| 64 | return vsha1pq_u32(hash_abcd, hash_e, wk); |
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| 65 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) |
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| 66 | } |
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| 67 | |
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| 68 | uint32x4_t test_vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) { |
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| 69 | // CHECK-LABEL: @test_vsha1mq_u32 |
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| 70 | return vsha1mq_u32(hash_abcd, hash_e, wk); |
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| 71 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) |
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| 72 | } |
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| 73 | |
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| 74 | uint32x4_t test_vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) { |
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| 75 | // CHECK-LABEL: @test_vsha1su0q_u32 |
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| 76 | return vsha1su0q_u32(w0_3, w4_7, w8_11); |
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| 77 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) |
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| 78 | } |
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| 79 | |
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| 80 | uint32x4_t test_vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) { |
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| 81 | // CHECK-LABEL: @test_vsha256hq_u32 |
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| 82 | return vsha256hq_u32(hash_abcd, hash_efgh, wk); |
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| 83 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) |
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| 84 | } |
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| 85 | |
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| 86 | uint32x4_t test_vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) { |
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| 87 | // CHECK-LABEL: @test_vsha256h2q_u32 |
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| 88 | return vsha256h2q_u32(hash_efgh, hash_abcd, wk); |
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| 89 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) |
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| 90 | } |
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| 91 | |
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| 92 | uint32x4_t test_vsha256su1q_u32(uint32x4_t w0_3, uint32x4_t w8_11, uint32x4_t w12_15) { |
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| 93 | // CHECK-LABEL: @test_vsha256su1q_u32 |
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| 94 | return vsha256su1q_u32(w0_3, w8_11, w12_15); |
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| 95 | // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) |
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| 96 | } |
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| 97 | |
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