TargetInfo.cpp source code [clang_source_code/lib/CodeGen/TargetInfo.cpp]

1	//===---- TargetInfo.cpp - Encapsulate target details ------------ C++ --===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// These classes wrap the information about a call or function
10	// definition used to handle ABI compliancy.
11	//
12	//===----------------------------------------------------------------------===//
13
14	#include "TargetInfo.h"
15	#include "ABIInfo.h"
16	#include "CGBlocks.h"
17	#include "CGCXXABI.h"
18	#include "CGValue.h"
19	#include "CodeGenFunction.h"
20	#include "clang/AST/RecordLayout.h"
21	#include "clang/Basic/CodeGenOptions.h"
22	#include "clang/CodeGen/CGFunctionInfo.h"
23	#include "clang/CodeGen/SwiftCallingConv.h"
24	#include "llvm/ADT/StringExtras.h"
25	#include "llvm/ADT/StringSwitch.h"
26	#include "llvm/ADT/Triple.h"
27	#include "llvm/ADT/Twine.h"
28	#include "llvm/IR/DataLayout.h"
29	#include "llvm/IR/Type.h"
30	#include "llvm/Support/raw_ostream.h"
31	#include <algorithm> // std::sort
32
33	using namespace clang;
34	using namespace CodeGen;
35
36	// Helper for coercing an aggregate argument or return value into an integer
37	// array of the same size (including padding) and alignment. This alternate
38	// coercion happens only for the RenderScript ABI and can be removed after
39	// runtimes that rely on it are no longer supported.
40	//
41	// RenderScript assumes that the size of the argument / return value in the IR
42	// is the same as the size of the corresponding qualified type. This helper
43	// coerces the aggregate type into an array of the same size (including
44	// padding). This coercion is used in lieu of expansion of struct members or
45	// other canonical coercions that return a coerced-type of larger size.
46	//
47	// Ty - The argument / return value type
48	// Context - The associated ASTContext
49	// LLVMContext - The associated LLVMContext
50	static ABIArgInfo coerceToIntArray(QualType Ty,
51	ASTContext &Context,
52	llvm::LLVMContext &LLVMContext) {
53	// Alignment and Size are measured in bits.
54	const uint64_t Size = Context.getTypeSize(Ty);
55	const uint64_t Alignment = Context.getTypeAlign(Ty);
56	llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
57	const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
58	return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
59	}
60
61	static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
62	llvm::Value *Array,
63	llvm::Value *Value,
64	unsigned FirstIndex,
65	unsigned LastIndex) {
66	// Alternatively, we could emit this as a loop in the source.
67	for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
68	llvm::Value *Cell =
69	Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
70	Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
71	}
72	}
73
74	static bool isAggregateTypeForABI(QualType T) {
75	return !CodeGenFunction::hasScalarEvaluationKind(T) \|\|
76	T->isMemberFunctionPointerType();
77	}
78
79	ABIArgInfo
80	ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
81	llvm::Type *Padding) const {
82	return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
83	ByRef, Realign, Padding);
84	}
85
86	ABIArgInfo
87	ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
88	return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
89	/ByRef/ false, Realign);
90	}
91
92	Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
93	QualType Ty) const {
94	return Address::invalid();
95	}
96
97	ABIInfo::~ABIInfo() {}
98
99	/// Does the given lowering require more than the given number of
100	/// registers when expanded?
101	///
102	/// This is intended to be the basis of a reasonable basic implementation
103	/// of should{Pass,Return}IndirectlyForSwift.
104	///
105	/// For most targets, a limit of four total registers is reasonable; this
106	/// limits the amount of code required in order to move around the value
107	/// in case it wasn't produced immediately prior to the call by the caller
108	/// (or wasn't produced in exactly the right registers) or isn't used
109	/// immediately within the callee. But some targets may need to further
110	/// limit the register count due to an inability to support that many
111	/// return registers.
112	static bool occupiesMoreThan(CodeGenTypes &cgt,
113	ArrayRef<llvm::Type*> scalarTypes,
114	unsigned maxAllRegisters) {
115	unsigned intCount = 0, fpCount = 0;
116	for (llvm::Type *type : scalarTypes) {
117	if (type->isPointerTy()) {
118	intCount++;
119	} else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
120	auto ptrWidth = cgt.getTarget().getPointerWidth(0);
121	intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
122	} else {
123	isVectorTy() \|\| type->isFloatingPointTy()", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 123, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(type->isVectorTy() \|\| type->isFloatingPointTy());
124	fpCount++;
125	}
126	}
127
128	return (intCount + fpCount > maxAllRegisters);
129	}
130
131	bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
132	llvm::Type *eltTy,
133	unsigned numElts) const {
134	// The default implementation of this assumes that the target guarantees
135	// 128-bit SIMD support but nothing more.
136	return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
137	}
138
139	static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
140	CGCXXABI &CXXABI) {
141	const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
142	if (!RD) {
143	if (!RT->getDecl()->canPassInRegisters())
144	return CGCXXABI::RAA_Indirect;
145	return CGCXXABI::RAA_Default;
146	}
147	return CXXABI.getRecordArgABI(RD);
148	}
149
150	static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
151	CGCXXABI &CXXABI) {
152	const RecordType *RT = T->getAs<RecordType>();
153	if (!RT)
154	return CGCXXABI::RAA_Default;
155	return getRecordArgABI(RT, CXXABI);
156	}
157
158	static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
159	const ABIInfo &Info) {
160	QualType Ty = FI.getReturnType();
161
162	if (const auto *RT = Ty->getAs<RecordType>())
163	if (!isa<CXXRecordDecl>(RT->getDecl()) &&
164	!RT->getDecl()->canPassInRegisters()) {
165	FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
166	return true;
167	}
168
169	return CXXABI.classifyReturnType(FI);
170	}
171
172	/// Pass transparent unions as if they were the type of the first element. Sema
173	/// should ensure that all elements of the union have the same "machine type".
174	static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
175	if (const RecordType *UT = Ty->getAsUnionType()) {
176	const RecordDecl *UD = UT->getDecl();
177	if (UD->hasAttr<TransparentUnionAttr>()) {
178	(0) . __assert_fail ("!UD->field_empty() && \"sema created an empty transparent union\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 178, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!UD->field_empty() && "sema created an empty transparent union");
179	return UD->field_begin()->getType();
180	}
181	}
182	return Ty;
183	}
184
185	CGCXXABI &ABIInfo::getCXXABI() const {
186	return CGT.getCXXABI();
187	}
188
189	ASTContext &ABIInfo::getContext() const {
190	return CGT.getContext();
191	}
192
193	llvm::LLVMContext &ABIInfo::getVMContext() const {
194	return CGT.getLLVMContext();
195	}
196
197	const llvm::DataLayout &ABIInfo::getDataLayout() const {
198	return CGT.getDataLayout();
199	}
200
201	const TargetInfo &ABIInfo::getTarget() const {
202	return CGT.getTarget();
203	}
204
205	const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
206	return CGT.getCodeGenOpts();
207	}
208
209	bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
210
211	bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
212	return false;
213	}
214
215	bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
216	uint64_t Members) const {
217	return false;
218	}
219
220	LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
221	raw_ostream &OS = llvm::errs();
222	OS << "(ABIArgInfo Kind=";
223	switch (TheKind) {
224	case Direct:
225	OS << "Direct Type=";
226	if (llvm::Type *Ty = getCoerceToType())
227	Ty->print(OS);
228	else
229	OS << "null";
230	break;
231	case Extend:
232	OS << "Extend";
233	break;
234	case Ignore:
235	OS << "Ignore";
236	break;
237	case InAlloca:
238	OS << "InAlloca Offset=" << getInAllocaFieldIndex();
239	break;
240	case Indirect:
241	OS << "Indirect Align=" << getIndirectAlign().getQuantity()
242	<< " ByVal=" << getIndirectByVal()
243	<< " Realign=" << getIndirectRealign();
244	break;
245	case Expand:
246	OS << "Expand";
247	break;
248	case CoerceAndExpand:
249	OS << "CoerceAndExpand Type=";
250	getCoerceAndExpandType()->print(OS);
251	break;
252	}
253	OS << ")\n";
254	}
255
256	// Dynamically round a pointer up to a multiple of the given alignment.
257	static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
258	llvm::Value *Ptr,
259	CharUnits Align) {
260	llvm::Value *PtrAsInt = Ptr;
261	// OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
262	PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
263	PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
264	llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
265	PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
266	llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
267	PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
268	Ptr->getType(),
269	Ptr->getName() + ".aligned");
270	return PtrAsInt;
271	}
272
273	/// Emit va_arg for a platform using the common void* representation,
274	/// where arguments are simply emitted in an array of slots on the stack.
275	///
276	/// This version implements the core direct-value passing rules.
277	///
278	/// \param SlotSize - The size and alignment of a stack slot.
279	/// Each argument will be allocated to a multiple of this number of
280	/// slots, and all the slots will be aligned to this value.
281	/// \param AllowHigherAlign - The slot alignment is not a cap;
282	/// an argument type with an alignment greater than the slot size
283	/// will be emitted on a higher-alignment address, potentially
284	/// leaving one or more empty slots behind as padding. If this
285	/// is false, the returned address might be less-aligned than
286	/// DirectAlign.
287	static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
288	Address VAListAddr,
289	llvm::Type *DirectTy,
290	CharUnits DirectSize,
291	CharUnits DirectAlign,
292	CharUnits SlotSize,
293	bool AllowHigherAlign) {
294	// Cast the element type to i8* if necessary. Some platforms define
295	// va_list as a struct containing an i8* instead of just an i8*.
296	if (VAListAddr.getElementType() != CGF.Int8PtrTy)
297	VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
298
299	llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
300
301	// If the CC aligns values higher than the slot size, do so if needed.
302	Address Addr = Address::invalid();
303	if (AllowHigherAlign && DirectAlign > SlotSize) {
304	Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
305	DirectAlign);
306	} else {
307	Addr = Address(Ptr, SlotSize);
308	}
309
310	// Advance the pointer past the argument, then store that back.
311	CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
312	Address NextPtr =
313	CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
314	CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
315
316	// If the argument is smaller than a slot, and this is a big-endian
317	// target, the argument will be right-adjusted in its slot.
318	if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
319	!DirectTy->isStructTy()) {
320	Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
321	}
322
323	Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
324	return Addr;
325	}
326
327	/// Emit va_arg for a platform using the common void* representation,
328	/// where arguments are simply emitted in an array of slots on the stack.
329	///
330	/// \param IsIndirect - Values of this type are passed indirectly.
331	/// \param ValueInfo - The size and alignment of this type, generally
332	/// computed with getContext().getTypeInfoInChars(ValueTy).
333	/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
334	/// Each argument will be allocated to a multiple of this number of
335	/// slots, and all the slots will be aligned to this value.
336	/// \param AllowHigherAlign - The slot alignment is not a cap;
337	/// an argument type with an alignment greater than the slot size
338	/// will be emitted on a higher-alignment address, potentially
339	/// leaving one or more empty slots behind as padding.
340	static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
341	QualType ValueTy, bool IsIndirect,
342	std::pair<CharUnits, CharUnits> ValueInfo,
343	CharUnits SlotSizeAndAlign,
344	bool AllowHigherAlign) {
345	// The size and alignment of the value that was passed directly.
346	CharUnits DirectSize, DirectAlign;
347	if (IsIndirect) {
348	DirectSize = CGF.getPointerSize();
349	DirectAlign = CGF.getPointerAlign();
350	} else {
351	DirectSize = ValueInfo.first;
352	DirectAlign = ValueInfo.second;
353	}
354
355	// Cast the address we've calculated to the right type.
356	llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
357	if (IsIndirect)
358	DirectTy = DirectTy->getPointerTo(0);
359
360	Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
361	DirectSize, DirectAlign,
362	SlotSizeAndAlign,
363	AllowHigherAlign);
364
365	if (IsIndirect) {
366	Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
367	}
368
369	return Addr;
370
371	}
372
373	static Address emitMergePHI(CodeGenFunction &CGF,
374	Address Addr1, llvm::BasicBlock *Block1,
375	Address Addr2, llvm::BasicBlock *Block2,
376	const llvm::Twine &Name = "") {
377	assert(Addr1.getType() == Addr2.getType());
378	llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
379	PHI->addIncoming(Addr1.getPointer(), Block1);
380	PHI->addIncoming(Addr2.getPointer(), Block2);
381	CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
382	return Address(PHI, Align);
383	}
384
385	TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; }
386
387	// If someone can figure out a general rule for this, that would be great.
388	// It's probably just doomed to be platform-dependent, though.
389	unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
390	// Verified for:
391	// x86-64 FreeBSD, Linux, Darwin
392	// x86-32 FreeBSD, Linux, Darwin
393	// PowerPC Linux, Darwin
394	// ARM Darwin (not EABI)
395	// AArch64 Linux
396	return 32;
397	}
398
399	bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
400	const FunctionNoProtoType *fnType) const {
401	// The following conventions are known to require this to be false:
402	// x86_stdcall
403	// MIPS
404	// For everything else, we just prefer false unless we opt out.
405	return false;
406	}
407
408	void
409	TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
410	llvm::SmallString<24> &Opt) const {
411	// This assumes the user is passing a library name like "rt" instead of a
412	// filename like "librt.a/so", and that they don't care whether it's static or
413	// dynamic.
414	Opt = "-l";
415	Opt += Lib;
416	}
417
418	unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
419	// OpenCL kernels are called via an explicit runtime API with arguments
420	// set with clSetKernelArg(), not as normal sub-functions.
421	// Return SPIR_KERNEL by default as the kernel calling convention to
422	// ensure the fingerprint is fixed such way that each OpenCL argument
423	// gets one matching argument in the produced kernel function argument
424	// list to enable feasible implementation of clSetKernelArg() with
425	// aggregates etc. In case we would use the default C calling conv here,
426	// clSetKernelArg() might break depending on the target-specific
427	// conventions; different targets might split structs passed as values
428	// to multiple function arguments etc.
429	return llvm::CallingConv::SPIR_KERNEL;
430	}
431
432	llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
433	llvm::PointerType *T, QualType QT) const {
434	return llvm::ConstantPointerNull::get(T);
435	}
436
437	LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
438	const VarDecl *D) const {
439	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 441, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!CGM.getLangOpts().OpenCL &&
440	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 441, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
441	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 441, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Address space agnostic languages only");
442	return D ? D->getType().getAddressSpace() : LangAS::Default;
443	}
444
445	llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
446	CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
447	LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
448	// Since target may map different address spaces in AST to the same address
449	// space, an address space conversion may end up as a bitcast.
450	if (auto *C = dyn_cast<llvm::Constant>(Src))
451	return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
452	return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
453	}
454
455	llvm::Constant *
456	TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
457	LangAS SrcAddr, LangAS DestAddr,
458	llvm::Type *DestTy) const {
459	// Since target may map different address spaces in AST to the same address
460	// space, an address space conversion may end up as a bitcast.
461	return llvm::ConstantExpr::getPointerCast(Src, DestTy);
462	}
463
464	llvm::SyncScope::ID
465	TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
466	SyncScope Scope,
467	llvm::AtomicOrdering Ordering,
468	llvm::LLVMContext &Ctx) const {
469	return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
470	}
471
472	static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
473
474	/// isEmptyField - Return true iff a the field is "empty", that is it
475	/// is an unnamed bit-field or an (array of) empty record(s).
476	static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
477	bool AllowArrays) {
478	if (FD->isUnnamedBitfield())
479	return true;
480
481	QualType FT = FD->getType();
482
483	// Constant arrays of empty records count as empty, strip them off.
484	// Constant arrays of zero length always count as empty.
485	if (AllowArrays)
486	while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
487	if (AT->getSize() == 0)
488	return true;
489	FT = AT->getElementType();
490	}
491
492	const RecordType *RT = FT->getAs<RecordType>();
493	if (!RT)
494	return false;
495
496	// C++ record fields are never empty, at least in the Itanium ABI.
497	//
498	// FIXME: We should use a predicate for whether this behavior is true in the
499	// current ABI.
500	if (isa<CXXRecordDecl>(RT->getDecl()))
501	return false;
502
503	return isEmptyRecord(Context, FT, AllowArrays);
504	}
505
506	/// isEmptyRecord - Return true iff a structure contains only empty
507	/// fields. Note that a structure with a flexible array member is not
508	/// considered empty.
509	static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
510	const RecordType *RT = T->getAs<RecordType>();
511	if (!RT)
512	return false;
513	const RecordDecl *RD = RT->getDecl();
514	if (RD->hasFlexibleArrayMember())
515	return false;
516
517	// If this is a C++ record, check the bases first.
518	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
519	for (const auto &I : CXXRD->bases())
520	if (!isEmptyRecord(Context, I.getType(), true))
521	return false;
522
523	for (const auto *I : RD->fields())
524	if (!isEmptyField(Context, I, AllowArrays))
525	return false;
526	return true;
527	}
528
529	/// isSingleElementStruct - Determine if a structure is a "single
530	/// element struct", i.e. it has exactly one non-empty field or
531	/// exactly one field which is itself a single element
532	/// struct. Structures with flexible array members are never
533	/// considered single element structs.
534	///
535	/// \return The field declaration for the single non-empty field, if
536	/// it exists.
537	static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
538	const RecordType *RT = T->getAs<RecordType>();
539	if (!RT)
540	return nullptr;
541
542	const RecordDecl *RD = RT->getDecl();
543	if (RD->hasFlexibleArrayMember())
544	return nullptr;
545
546	const Type *Found = nullptr;
547
548	// If this is a C++ record, check the bases first.
549	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
550	for (const auto &I : CXXRD->bases()) {
551	// Ignore empty records.
552	if (isEmptyRecord(Context, I.getType(), true))
553	continue;
554
555	// If we already found an element then this isn't a single-element struct.
556	if (Found)
557	return nullptr;
558
559	// If this is non-empty and not a single element struct, the composite
560	// cannot be a single element struct.
561	Found = isSingleElementStruct(I.getType(), Context);
562	if (!Found)
563	return nullptr;
564	}
565	}
566
567	// Check for single element.
568	for (const auto *FD : RD->fields()) {
569	QualType FT = FD->getType();
570
571	// Ignore empty fields.
572	if (isEmptyField(Context, FD, true))
573	continue;
574
575	// If we already found an element then this isn't a single-element
576	// struct.
577	if (Found)
578	return nullptr;
579
580	// Treat single element arrays as the element.
581	while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
582	if (AT->getSize().getZExtValue() != 1)
583	break;
584	FT = AT->getElementType();
585	}
586
587	if (!isAggregateTypeForABI(FT)) {
588	Found = FT.getTypePtr();
589	} else {
590	Found = isSingleElementStruct(FT, Context);
591	if (!Found)
592	return nullptr;
593	}
594	}
595
596	// We don't consider a struct a single-element struct if it has
597	// padding beyond the element type.
598	if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
599	return nullptr;
600
601	return Found;
602	}
603
604	namespace {
605	Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
606	const ABIArgInfo &AI) {
607	// This default implementation defers to the llvm backend's va_arg
608	// instruction. It can handle only passing arguments directly
609	// (typically only handled in the backend for primitive types), or
610	// aggregates passed indirectly by pointer (NOTE: if the "byval"
611	// flag has ABI impact in the callee, this implementation cannot
612	// work.)
613
614	// Only a few cases are covered here at the moment -- those needed
615	// by the default abi.
616	llvm::Value *Val;
617
618	if (AI.isIndirect()) {
619	(0) . __assert_fail ("!AI.getPaddingType() && \"Unexpected PaddingType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 620, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!AI.getPaddingType() &&
620	(0) . __assert_fail ("!AI.getPaddingType() && \"Unexpected PaddingType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 620, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
621	(0) . __assert_fail ("!AI.getIndirectRealign() && \"Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 623, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(
622	(0) . __assert_fail ("!AI.getIndirectRealign() && \"Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 623, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> !AI.getIndirectRealign() &&
623	(0) . __assert_fail ("!AI.getIndirectRealign() && \"Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 623, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
624
625	auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
626	CharUnits TyAlignForABI = TyInfo.second;
627
628	llvm::Type *BaseTy =
629	llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
630	llvm::Value *Addr =
631	CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
632	return Address(Addr, TyAlignForABI);
633	} else {
634	(0) . __assert_fail ("(AI.isDirect() \|\| AI.isExtend()) && \"Unexpected ArgInfo Kind in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 635, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((AI.isDirect() \|\| AI.isExtend()) &&
635	(0) . __assert_fail ("(AI.isDirect() \|\| AI.isExtend()) && \"Unexpected ArgInfo Kind in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 635, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected ArgInfo Kind in generic VAArg emitter!");
636
637	(0) . __assert_fail ("!AI.getInReg() && \"Unexpected InReg seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 638, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!AI.getInReg() &&
638	(0) . __assert_fail ("!AI.getInReg() && \"Unexpected InReg seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 638, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected InReg seen in arginfo in generic VAArg emitter!");
639	(0) . __assert_fail ("!AI.getPaddingType() && \"Unexpected PaddingType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 640, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!AI.getPaddingType() &&
640	(0) . __assert_fail ("!AI.getPaddingType() && \"Unexpected PaddingType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 640, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
641	(0) . __assert_fail ("!AI.getDirectOffset() && \"Unexpected DirectOffset seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 642, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!AI.getDirectOffset() &&
642	(0) . __assert_fail ("!AI.getDirectOffset() && \"Unexpected DirectOffset seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 642, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
643	(0) . __assert_fail ("!AI.getCoerceToType() && \"Unexpected CoerceToType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 644, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!AI.getCoerceToType() &&
644	(0) . __assert_fail ("!AI.getCoerceToType() && \"Unexpected CoerceToType seen in arginfo in generic VAArg emitter!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 644, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
645
646	Address Temp = CGF.CreateMemTemp(Ty, "varet");
647	Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
648	CGF.Builder.CreateStore(Val, Temp);
649	return Temp;
650	}
651	}
652
653	/// DefaultABIInfo - The default implementation for ABI specific
654	/// details. This implementation provides information which results in
655	/// self-consistent and sensible LLVM IR generation, but does not
656	/// conform to any particular ABI.
657	class DefaultABIInfo : public ABIInfo {
658	public:
659	DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
660
661	ABIArgInfo classifyReturnType(QualType RetTy) const;
662	ABIArgInfo classifyArgumentType(QualType RetTy) const;
663
664	void computeInfo(CGFunctionInfo &FI) const override {
665	if (!getCXXABI().classifyReturnType(FI))
666	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
667	for (auto &I : FI.arguments())
668	I.info = classifyArgumentType(I.type);
669	}
670
671	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
672	QualType Ty) const override {
673	return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
674	}
675	};
676
677	class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
678	public:
679	DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
680	: TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
681	};
682
683	ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
684	Ty = useFirstFieldIfTransparentUnion(Ty);
685
686	if (isAggregateTypeForABI(Ty)) {
687	// Records with non-trivial destructors/copy-constructors should not be
688	// passed by value.
689	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
690	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
691
692	return getNaturalAlignIndirect(Ty);
693	}
694
695	// Treat an enum type as its underlying type.
696	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
697	Ty = EnumTy->getDecl()->getIntegerType();
698
699	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
700	: ABIArgInfo::getDirect());
701	}
702
703	ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
704	if (RetTy->isVoidType())
705	return ABIArgInfo::getIgnore();
706
707	if (isAggregateTypeForABI(RetTy))
708	return getNaturalAlignIndirect(RetTy);
709
710	// Treat an enum type as its underlying type.
711	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
712	RetTy = EnumTy->getDecl()->getIntegerType();
713
714	return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
715	: ABIArgInfo::getDirect());
716	}
717
718	//===----------------------------------------------------------------------===//
719	// WebAssembly ABI Implementation
720	//
721	// This is a very simple ABI that relies a lot on DefaultABIInfo.
722	//===----------------------------------------------------------------------===//
723
724	class WebAssemblyABIInfo final : public SwiftABIInfo {
725	DefaultABIInfo defaultInfo;
726
727	public:
728	explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
729	: SwiftABIInfo(CGT), defaultInfo(CGT) {}
730
731	private:
732	ABIArgInfo classifyReturnType(QualType RetTy) const;
733	ABIArgInfo classifyArgumentType(QualType Ty) const;
734
735	// DefaultABIInfo's classifyReturnType and classifyArgumentType are
736	// non-virtual, but computeInfo and EmitVAArg are virtual, so we
737	// overload them.
738	void computeInfo(CGFunctionInfo &FI) const override {
739	if (!getCXXABI().classifyReturnType(FI))
740	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
741	for (auto &Arg : FI.arguments())
742	Arg.info = classifyArgumentType(Arg.type);
743	}
744
745	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
746	QualType Ty) const override;
747
748	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
749	bool asReturnValue) const override {
750	return occupiesMoreThan(CGT, scalars, /total/ 4);
751	}
752
753	bool isSwiftErrorInRegister() const override {
754	return false;
755	}
756	};
757
758	class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
759	public:
760	explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
761	: TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
762
763	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
764	CodeGen::CodeGenModule &CGM) const override {
765	TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
766	if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
767	if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
768	llvm::Function *Fn = cast<llvm::Function>(GV);
769	llvm::AttrBuilder B;
770	B.addAttribute("wasm-import-module", Attr->getImportModule());
771	Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
772	}
773	if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
774	llvm::Function *Fn = cast<llvm::Function>(GV);
775	llvm::AttrBuilder B;
776	B.addAttribute("wasm-import-name", Attr->getImportName());
777	Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
778	}
779	}
780
781	if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
782	llvm::Function *Fn = cast<llvm::Function>(GV);
783	if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
784	Fn->addFnAttr("no-prototype");
785	}
786	}
787	};
788
789	/// Classify argument of given type \p Ty.
790	ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
791	Ty = useFirstFieldIfTransparentUnion(Ty);
792
793	if (isAggregateTypeForABI(Ty)) {
794	// Records with non-trivial destructors/copy-constructors should not be
795	// passed by value.
796	if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
797	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
798	// Ignore empty structs/unions.
799	if (isEmptyRecord(getContext(), Ty, true))
800	return ABIArgInfo::getIgnore();
801	// Lower single-element structs to just pass a regular value. TODO: We
802	// could do reasonable-size multiple-element structs too, using getExpand(),
803	// though watch out for things like bitfields.
804	if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
805	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
806	}
807
808	// Otherwise just do the default thing.
809	return defaultInfo.classifyArgumentType(Ty);
810	}
811
812	ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
813	if (isAggregateTypeForABI(RetTy)) {
814	// Records with non-trivial destructors/copy-constructors should not be
815	// returned by value.
816	if (!getRecordArgABI(RetTy, getCXXABI())) {
817	// Ignore empty structs/unions.
818	if (isEmptyRecord(getContext(), RetTy, true))
819	return ABIArgInfo::getIgnore();
820	// Lower single-element structs to just return a regular value. TODO: We
821	// could do reasonable-size multiple-element structs too, using
822	// ABIArgInfo::getDirect().
823	if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
824	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
825	}
826	}
827
828	// Otherwise just do the default thing.
829	return defaultInfo.classifyReturnType(RetTy);
830	}
831
832	Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
833	QualType Ty) const {
834	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /Indirect=/ false,
835	getContext().getTypeInfoInChars(Ty),
836	CharUnits::fromQuantity(4),
837	/AllowHigherAlign=/ true);
838	}
839
840	//===----------------------------------------------------------------------===//
841	// le32/PNaCl bitcode ABI Implementation
842	//
843	// This is a simplified version of the x86_32 ABI. Arguments and return values
844	// are always passed on the stack.
845	//===----------------------------------------------------------------------===//
846
847	class PNaClABIInfo : public ABIInfo {
848	public:
849	PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
850
851	ABIArgInfo classifyReturnType(QualType RetTy) const;
852	ABIArgInfo classifyArgumentType(QualType RetTy) const;
853
854	void computeInfo(CGFunctionInfo &FI) const override;
855	Address EmitVAArg(CodeGenFunction &CGF,
856	Address VAListAddr, QualType Ty) const override;
857	};
858
859	class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
860	public:
861	PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
862	: TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
863	};
864
865	void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
866	if (!getCXXABI().classifyReturnType(FI))
867	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
868
869	for (auto &I : FI.arguments())
870	I.info = classifyArgumentType(I.type);
871	}
872
873	Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
874	QualType Ty) const {
875	// The PNaCL ABI is a bit odd, in that varargs don't use normal
876	// function classification. Structs get passed directly for varargs
877	// functions, through a rewriting transform in
878	// pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
879	// this target to actually support a va_arg instructions with an
880	// aggregate type, unlike other targets.
881	return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
882	}
883
884	/// Classify argument of given type \p Ty.
885	ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
886	if (isAggregateTypeForABI(Ty)) {
887	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
888	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
889	return getNaturalAlignIndirect(Ty);
890	} else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
891	// Treat an enum type as its underlying type.
892	Ty = EnumTy->getDecl()->getIntegerType();
893	} else if (Ty->isFloatingType()) {
894	// Floating-point types don't go inreg.
895	return ABIArgInfo::getDirect();
896	}
897
898	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
899	: ABIArgInfo::getDirect());
900	}
901
902	ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
903	if (RetTy->isVoidType())
904	return ABIArgInfo::getIgnore();
905
906	// In the PNaCl ABI we always return records/structures on the stack.
907	if (isAggregateTypeForABI(RetTy))
908	return getNaturalAlignIndirect(RetTy);
909
910	// Treat an enum type as its underlying type.
911	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
912	RetTy = EnumTy->getDecl()->getIntegerType();
913
914	return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
915	: ABIArgInfo::getDirect());
916	}
917
918	/// IsX86_MMXType - Return true if this is an MMX type.
919	bool IsX86_MMXType(llvm::Type *IRType) {
920	// Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
921	return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
922	cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
923	IRType->getScalarSizeInBits() != 64;
924	}
925
926	static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
927	StringRef Constraint,
928	llvm::Type* Ty) {
929	bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
930	.Cases("y", "&y", "^Ym", true)
931	.Default(false);
932	if (IsMMXCons && Ty->isVectorTy()) {
933	if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
934	// Invalid MMX constraint
935	return nullptr;
936	}
937
938	return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
939	}
940
941	// No operation needed
942	return Ty;
943	}
944
945	/// Returns true if this type can be passed in SSE registers with the
946	/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
947	static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
948	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
949	if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
950	if (BT->getKind() == BuiltinType::LongDouble) {
951	if (&Context.getTargetInfo().getLongDoubleFormat() ==
952	&llvm::APFloat::x87DoubleExtended())
953	return false;
954	}
955	return true;
956	}
957	} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
958	// vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
959	// registers specially.
960	unsigned VecSize = Context.getTypeSize(VT);
961	if (VecSize == 128 \|\| VecSize == 256 \|\| VecSize == 512)
962	return true;
963	}
964	return false;
965	}
966
967	/// Returns true if this aggregate is small enough to be passed in SSE registers
968	/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
969	static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
970	return NumMembers <= 4;
971	}
972
973	/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
974	static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
975	auto AI = ABIArgInfo::getDirect(T);
976	AI.setInReg(true);
977	AI.setCanBeFlattened(false);
978	return AI;
979	}
980
981	//===----------------------------------------------------------------------===//
982	// X86-32 ABI Implementation
983	//===----------------------------------------------------------------------===//
984
985	/// Similar to llvm::CCState, but for Clang.
986	struct CCState {
987	CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
988
989	unsigned CC;
990	unsigned FreeRegs;
991	unsigned FreeSSERegs;
992	};
993
994	enum {
995	// Vectorcall only allows the first 6 parameters to be passed in registers.
996	VectorcallMaxParamNumAsReg = 6
997	};
998
999	/// X86_32ABIInfo - The X86-32 ABI information.
1000	class X86_32ABIInfo : public SwiftABIInfo {
1001	enum Class {
1002	Integer,
1003	Float
1004	};
1005
1006	static const unsigned MinABIStackAlignInBytes = 4;
1007
1008	bool IsDarwinVectorABI;
1009	bool IsRetSmallStructInRegABI;
1010	bool IsWin32StructABI;
1011	bool IsSoftFloatABI;
1012	bool IsMCUABI;
1013	unsigned DefaultNumRegisterParameters;
1014
1015	static bool isRegisterSize(unsigned Size) {
1016	return (Size == 8 \|\| Size == 16 \|\| Size == 32 \|\| Size == 64);
1017	}
1018
1019	bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1020	// FIXME: Assumes vectorcall is in use.
1021	return isX86VectorTypeForVectorCall(getContext(), Ty);
1022	}
1023
1024	bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1025	uint64_t NumMembers) const override {
1026	// FIXME: Assumes vectorcall is in use.
1027	return isX86VectorCallAggregateSmallEnough(NumMembers);
1028	}
1029
1030	bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1031
1032	/// getIndirectResult - Give a source type \arg Ty, return a suitable result
1033	/// such that the argument will be passed in memory.
1034	ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1035
1036	ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1037
1038	/// Return the alignment to use for the given type on the stack.
1039	unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1040
1041	Class classify(QualType Ty) const;
1042	ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1043	ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1044
1045	/// Updates the number of available free registers, returns
1046	/// true if any registers were allocated.
1047	bool updateFreeRegs(QualType Ty, CCState &State) const;
1048
1049	bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1050	bool &NeedsPadding) const;
1051	bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1052
1053	bool canExpandIndirectArgument(QualType Ty) const;
1054
1055	/// Rewrite the function info so that all memory arguments use
1056	/// inalloca.
1057	void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1058
1059	void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1060	CharUnits &StackOffset, ABIArgInfo &Info,
1061	QualType Type) const;
1062	void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1063	bool &UsedInAlloca) const;
1064
1065	public:
1066
1067	void computeInfo(CGFunctionInfo &FI) const override;
1068	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1069	QualType Ty) const override;
1070
1071	X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1072	bool RetSmallStructInRegABI, bool Win32StructABI,
1073	unsigned NumRegisterParameters, bool SoftFloatABI)
1074	: SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1075	IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1076	IsWin32StructABI(Win32StructABI),
1077	IsSoftFloatABI(SoftFloatABI),
1078	IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1079	DefaultNumRegisterParameters(NumRegisterParameters) {}
1080
1081	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1082	bool asReturnValue) const override {
1083	// LLVM's x86-32 lowering currently only assigns up to three
1084	// integer registers and three fp registers. Oddly, it'll use up to
1085	// four vector registers for vectors, but those can overlap with the
1086	// scalar registers.
1087	return occupiesMoreThan(CGT, scalars, /total/ 3);
1088	}
1089
1090	bool isSwiftErrorInRegister() const override {
1091	// x86-32 lowering does not support passing swifterror in a register.
1092	return false;
1093	}
1094	};
1095
1096	class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1097	public:
1098	X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1099	bool RetSmallStructInRegABI, bool Win32StructABI,
1100	unsigned NumRegisterParameters, bool SoftFloatABI)
1101	: TargetCodeGenInfo(new X86_32ABIInfo(
1102	CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1103	NumRegisterParameters, SoftFloatABI)) {}
1104
1105	static bool isStructReturnInRegABI(
1106	const llvm::Triple &Triple, const CodeGenOptions &Opts);
1107
1108	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
1109	CodeGen::CodeGenModule &CGM) const override;
1110
1111	int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1112	// Darwin uses different dwarf register numbers for EH.
1113	if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1114	return 4;
1115	}
1116
1117	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1118	llvm::Value *Address) const override;
1119
1120	llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1121	StringRef Constraint,
1122	llvm::Type* Ty) const override {
1123	return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1124	}
1125
1126	void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1127	std::string &Constraints,
1128	std::vector<llvm::Type *> &ResultRegTypes,
1129	std::vector<llvm::Type *> &ResultTruncRegTypes,
1130	std::vector<LValue> &ResultRegDests,
1131	std::string &AsmString,
1132	unsigned NumOutputs) const override;
1133
1134	llvm::Constant *
1135	getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1136	unsigned Sig = (0xeb << 0) \| // jmp rel8
1137	(0x06 << 8) \| // .+0x08
1138	('v' << 16) \|
1139	('2' << 24);
1140	return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1141	}
1142
1143	StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1144	return "movl\t%ebp, %ebp"
1145	"\t\t// marker for objc_retainAutoreleaseReturnValue";
1146	}
1147	};
1148
1149	}
1150
1151	/// Rewrite input constraint references after adding some output constraints.
1152	/// In the case where there is one output and one input and we add one output,
1153	/// we need to replace all operand references greater than or equal to 1:
1154	/// mov $0, $1
1155	/// mov eax, $1
1156	/// The result will be:
1157	/// mov $0, $2
1158	/// mov eax, $2
1159	static void rewriteInputConstraintReferences(unsigned FirstIn,
1160	unsigned NumNewOuts,
1161	std::string &AsmString) {
1162	std::string Buf;
1163	llvm::raw_string_ostream OS(Buf);
1164	size_t Pos = 0;
1165	while (Pos < AsmString.size()) {
1166	size_t DollarStart = AsmString.find('$', Pos);
1167	if (DollarStart == std::string::npos)
1168	DollarStart = AsmString.size();
1169	size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1170	if (DollarEnd == std::string::npos)
1171	DollarEnd = AsmString.size();
1172	OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1173	Pos = DollarEnd;
1174	size_t NumDollars = DollarEnd - DollarStart;
1175	if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1176	// We have an operand reference.
1177	size_t DigitStart = Pos;
1178	size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1179	if (DigitEnd == std::string::npos)
1180	DigitEnd = AsmString.size();
1181	StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1182	unsigned OperandIndex;
1183	if (!OperandStr.getAsInteger(10, OperandIndex)) {
1184	if (OperandIndex >= FirstIn)
1185	OperandIndex += NumNewOuts;
1186	OS << OperandIndex;
1187	} else {
1188	OS << OperandStr;
1189	}
1190	Pos = DigitEnd;
1191	}
1192	}
1193	AsmString = std::move(OS.str());
1194	}
1195
1196	/// Add output constraints for EAX:EDX because they are return registers.
1197	void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1198	CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1199	std::vector<llvm::Type *> &ResultRegTypes,
1200	std::vector<llvm::Type *> &ResultTruncRegTypes,
1201	std::vector<LValue> &ResultRegDests, std::string &AsmString,
1202	unsigned NumOutputs) const {
1203	uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1204
1205	// Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1206	// larger.
1207	if (!Constraints.empty())
1208	Constraints += ',';
1209	if (RetWidth <= 32) {
1210	Constraints += "={eax}";
1211	ResultRegTypes.push_back(CGF.Int32Ty);
1212	} else {
1213	// Use the 'A' constraint for EAX:EDX.
1214	Constraints += "=A";
1215	ResultRegTypes.push_back(CGF.Int64Ty);
1216	}
1217
1218	// Truncate EAX or EAX:EDX to an integer of the appropriate size.
1219	llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1220	ResultTruncRegTypes.push_back(CoerceTy);
1221
1222	// Coerce the integer by bitcasting the return slot pointer.
1223	ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1224	CoerceTy->getPointerTo()));
1225	ResultRegDests.push_back(ReturnSlot);
1226
1227	rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1228	}
1229
1230	/// shouldReturnTypeInRegister - Determine if the given type should be
1231	/// returned in a register (for the Darwin and MCU ABI).
1232	bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1233	ASTContext &Context) const {
1234	uint64_t Size = Context.getTypeSize(Ty);
1235
1236	// For i386, type must be register sized.
1237	// For the MCU ABI, it only needs to be <= 8-byte
1238	if ((IsMCUABI && Size > 64) \|\| (!IsMCUABI && !isRegisterSize(Size)))
1239	return false;
1240
1241	if (Ty->isVectorType()) {
1242	// 64- and 128- bit vectors inside structures are not returned in
1243	// registers.
1244	if (Size == 64 \|\| Size == 128)
1245	return false;
1246
1247	return true;
1248	}
1249
1250	// If this is a builtin, pointer, enum, complex type, member pointer, or
1251	// member function pointer it is ok.
1252	if (Ty->getAs<BuiltinType>() \|\| Ty->hasPointerRepresentation() \|\|
1253	Ty->isAnyComplexType() \|\| Ty->isEnumeralType() \|\|
1254	Ty->isBlockPointerType() \|\| Ty->isMemberPointerType())
1255	return true;
1256
1257	// Arrays are treated like records.
1258	if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1259	return shouldReturnTypeInRegister(AT->getElementType(), Context);
1260
1261	// Otherwise, it must be a record type.
1262	const RecordType *RT = Ty->getAs<RecordType>();
1263	if (!RT) return false;
1264
1265	// FIXME: Traverse bases here too.
1266
1267	// Structure types are passed in register if all fields would be
1268	// passed in a register.
1269	for (const auto *FD : RT->getDecl()->fields()) {
1270	// Empty fields are ignored.
1271	if (isEmptyField(Context, FD, true))
1272	continue;
1273
1274	// Check fields recursively.
1275	if (!shouldReturnTypeInRegister(FD->getType(), Context))
1276	return false;
1277	}
1278	return true;
1279	}
1280
1281	static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1282	// Treat complex types as the element type.
1283	if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1284	Ty = CTy->getElementType();
1285
1286	// Check for a type which we know has a simple scalar argument-passing
1287	// convention without any padding. (We're specifically looking for 32
1288	// and 64-bit integer and integer-equivalents, float, and double.)
1289	if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1290	!Ty->isEnumeralType() && !Ty->isBlockPointerType())
1291	return false;
1292
1293	uint64_t Size = Context.getTypeSize(Ty);
1294	return Size == 32 \|\| Size == 64;
1295	}
1296
1297	static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1298	uint64_t &Size) {
1299	for (const auto *FD : RD->fields()) {
1300	// Scalar arguments on the stack get 4 byte alignment on x86. If the
1301	// argument is smaller than 32-bits, expanding the struct will create
1302	// alignment padding.
1303	if (!is32Or64BitBasicType(FD->getType(), Context))
1304	return false;
1305
1306	// FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1307	// how to expand them yet, and the predicate for telling if a bitfield still
1308	// counts as "basic" is more complicated than what we were doing previously.
1309	if (FD->isBitField())
1310	return false;
1311
1312	Size += Context.getTypeSize(FD->getType());
1313	}
1314	return true;
1315	}
1316
1317	static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1318	uint64_t &Size) {
1319	// Don't do this if there are any non-empty bases.
1320	for (const CXXBaseSpecifier &Base : RD->bases()) {
1321	if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1322	Size))
1323	return false;
1324	}
1325	if (!addFieldSizes(Context, RD, Size))
1326	return false;
1327	return true;
1328	}
1329
1330	/// Test whether an argument type which is to be passed indirectly (on the
1331	/// stack) would have the equivalent layout if it was expanded into separate
1332	/// arguments. If so, we prefer to do the latter to avoid inhibiting
1333	/// optimizations.
1334	bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1335	// We can only expand structure types.
1336	const RecordType *RT = Ty->getAs<RecordType>();
1337	if (!RT)
1338	return false;
1339	const RecordDecl *RD = RT->getDecl();
1340	uint64_t Size = 0;
1341	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1342	if (!IsWin32StructABI) {
1343	// On non-Windows, we have to conservatively match our old bitcode
1344	// prototypes in order to be ABI-compatible at the bitcode level.
1345	if (!CXXRD->isCLike())
1346	return false;
1347	} else {
1348	// Don't do this for dynamic classes.
1349	if (CXXRD->isDynamicClass())
1350	return false;
1351	}
1352	if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1353	return false;
1354	} else {
1355	if (!addFieldSizes(getContext(), RD, Size))
1356	return false;
1357	}
1358
1359	// We can do this if there was no alignment padding.
1360	return Size == getContext().getTypeSize(Ty);
1361	}
1362
1363	ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1364	// If the return value is indirect, then the hidden argument is consuming one
1365	// integer register.
1366	if (State.FreeRegs) {
1367	--State.FreeRegs;
1368	if (!IsMCUABI)
1369	return getNaturalAlignIndirectInReg(RetTy);
1370	}
1371	return getNaturalAlignIndirect(RetTy, /ByVal=/false);
1372	}
1373
1374	ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1375	CCState &State) const {
1376	if (RetTy->isVoidType())
1377	return ABIArgInfo::getIgnore();
1378
1379	const Type *Base = nullptr;
1380	uint64_t NumElts = 0;
1381	if ((State.CC == llvm::CallingConv::X86_VectorCall \|\|
1382	State.CC == llvm::CallingConv::X86_RegCall) &&
1383	isHomogeneousAggregate(RetTy, Base, NumElts)) {
1384	// The LLVM struct type for such an aggregate should lower properly.
1385	return ABIArgInfo::getDirect();
1386	}
1387
1388	if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1389	// On Darwin, some vectors are returned in registers.
1390	if (IsDarwinVectorABI) {
1391	uint64_t Size = getContext().getTypeSize(RetTy);
1392
1393	// 128-bit vectors are a special case; they are returned in
1394	// registers and we need to make sure to pick a type the LLVM
1395	// backend will like.
1396	if (Size == 128)
1397	return ABIArgInfo::getDirect(llvm::VectorType::get(
1398	llvm::Type::getInt64Ty(getVMContext()), 2));
1399
1400	// Always return in register if it fits in a general purpose
1401	// register, or if it is 64 bits and has a single element.
1402	if ((Size == 8 \|\| Size == 16 \|\| Size == 32) \|\|
1403	(Size == 64 && VT->getNumElements() == 1))
1404	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1405	Size));
1406
1407	return getIndirectReturnResult(RetTy, State);
1408	}
1409
1410	return ABIArgInfo::getDirect();
1411	}
1412
1413	if (isAggregateTypeForABI(RetTy)) {
1414	if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1415	// Structures with flexible arrays are always indirect.
1416	if (RT->getDecl()->hasFlexibleArrayMember())
1417	return getIndirectReturnResult(RetTy, State);
1418	}
1419
1420	// If specified, structs and unions are always indirect.
1421	if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1422	return getIndirectReturnResult(RetTy, State);
1423
1424	// Ignore empty structs/unions.
1425	if (isEmptyRecord(getContext(), RetTy, true))
1426	return ABIArgInfo::getIgnore();
1427
1428	// Small structures which are register sized are generally returned
1429	// in a register.
1430	if (shouldReturnTypeInRegister(RetTy, getContext())) {
1431	uint64_t Size = getContext().getTypeSize(RetTy);
1432
1433	// As a special-case, if the struct is a "single-element" struct, and
1434	// the field is of type "float" or "double", return it in a
1435	// floating-point register. (MSVC does not apply this special case.)
1436	// We apply a similar transformation for pointer types to improve the
1437	// quality of the generated IR.
1438	if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1439	if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1440	\|\| SeltTy->hasPointerRepresentation())
1441	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1442
1443	// FIXME: We should be able to narrow this integer in cases with dead
1444	// padding.
1445	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1446	}
1447
1448	return getIndirectReturnResult(RetTy, State);
1449	}
1450
1451	// Treat an enum type as its underlying type.
1452	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1453	RetTy = EnumTy->getDecl()->getIntegerType();
1454
1455	return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1456	: ABIArgInfo::getDirect());
1457	}
1458
1459	static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1460	return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1461	}
1462
1463	static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1464	const RecordType *RT = Ty->getAs<RecordType>();
1465	if (!RT)
1466	return 0;
1467	const RecordDecl *RD = RT->getDecl();
1468
1469	// If this is a C++ record, check the bases first.
1470	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1471	for (const auto &I : CXXRD->bases())
1472	if (!isRecordWithSSEVectorType(Context, I.getType()))
1473	return false;
1474
1475	for (const auto *i : RD->fields()) {
1476	QualType FT = i->getType();
1477
1478	if (isSSEVectorType(Context, FT))
1479	return true;
1480
1481	if (isRecordWithSSEVectorType(Context, FT))
1482	return true;
1483	}
1484
1485	return false;
1486	}
1487
1488	unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1489	unsigned Align) const {
1490	// Otherwise, if the alignment is less than or equal to the minimum ABI
1491	// alignment, just use the default; the backend will handle this.
1492	if (Align <= MinABIStackAlignInBytes)
1493	return 0; // Use default alignment.
1494
1495	// On non-Darwin, the stack type alignment is always 4.
1496	if (!IsDarwinVectorABI) {
1497	// Set explicit alignment, since we may need to realign the top.
1498	return MinABIStackAlignInBytes;
1499	}
1500
1501	// Otherwise, if the type contains an SSE vector type, the alignment is 16.
1502	if (Align >= 16 && (isSSEVectorType(getContext(), Ty) \|\|
1503	isRecordWithSSEVectorType(getContext(), Ty)))
1504	return 16;
1505
1506	return MinABIStackAlignInBytes;
1507	}
1508
1509	ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1510	CCState &State) const {
1511	if (!ByVal) {
1512	if (State.FreeRegs) {
1513	--State.FreeRegs; // Non-byval indirects just use one pointer.
1514	if (!IsMCUABI)
1515	return getNaturalAlignIndirectInReg(Ty);
1516	}
1517	return getNaturalAlignIndirect(Ty, false);
1518	}
1519
1520	// Compute the byval alignment.
1521	unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1522	unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1523	if (StackAlign == 0)
1524	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /ByVal=/true);
1525
1526	// If the stack alignment is less than the type alignment, realign the
1527	// argument.
1528	bool Realign = TypeAlign > StackAlign;
1529	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1530	/ByVal=/true, Realign);
1531	}
1532
1533	X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1534	const Type *T = isSingleElementStruct(Ty, getContext());
1535	if (!T)
1536	T = Ty.getTypePtr();
1537
1538	if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1539	BuiltinType::Kind K = BT->getKind();
1540	if (K == BuiltinType::Float \|\| K == BuiltinType::Double)
1541	return Float;
1542	}
1543	return Integer;
1544	}
1545
1546	bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1547	if (!IsSoftFloatABI) {
1548	Class C = classify(Ty);
1549	if (C == Float)
1550	return false;
1551	}
1552
1553	unsigned Size = getContext().getTypeSize(Ty);
1554	unsigned SizeInRegs = (Size + 31) / 32;
1555
1556	if (SizeInRegs == 0)
1557	return false;
1558
1559	if (!IsMCUABI) {
1560	if (SizeInRegs > State.FreeRegs) {
1561	State.FreeRegs = 0;
1562	return false;
1563	}
1564	} else {
1565	// The MCU psABI allows passing parameters in-reg even if there are
1566	// earlier parameters that are passed on the stack. Also,
1567	// it does not allow passing >8-byte structs in-register,
1568	// even if there are 3 free registers available.
1569	if (SizeInRegs > State.FreeRegs \|\| SizeInRegs > 2)
1570	return false;
1571	}
1572
1573	State.FreeRegs -= SizeInRegs;
1574	return true;
1575	}
1576
1577	bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1578	bool &InReg,
1579	bool &NeedsPadding) const {
1580	// On Windows, aggregates other than HFAs are never passed in registers, and
1581	// they do not consume register slots. Homogenous floating-point aggregates
1582	// (HFAs) have already been dealt with at this point.
1583	if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1584	return false;
1585
1586	NeedsPadding = false;
1587	InReg = !IsMCUABI;
1588
1589	if (!updateFreeRegs(Ty, State))
1590	return false;
1591
1592	if (IsMCUABI)
1593	return true;
1594
1595	if (State.CC == llvm::CallingConv::X86_FastCall \|\|
1596	State.CC == llvm::CallingConv::X86_VectorCall \|\|
1597	State.CC == llvm::CallingConv::X86_RegCall) {
1598	if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1599	NeedsPadding = true;
1600
1601	return false;
1602	}
1603
1604	return true;
1605	}
1606
1607	bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1608	if (!updateFreeRegs(Ty, State))
1609	return false;
1610
1611	if (IsMCUABI)
1612	return false;
1613
1614	if (State.CC == llvm::CallingConv::X86_FastCall \|\|
1615	State.CC == llvm::CallingConv::X86_VectorCall \|\|
1616	State.CC == llvm::CallingConv::X86_RegCall) {
1617	if (getContext().getTypeSize(Ty) > 32)
1618	return false;
1619
1620	return (Ty->isIntegralOrEnumerationType() \|\| Ty->isPointerType() \|\|
1621	Ty->isReferenceType());
1622	}
1623
1624	return true;
1625	}
1626
1627	ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1628	CCState &State) const {
1629	// FIXME: Set alignment on indirect arguments.
1630
1631	Ty = useFirstFieldIfTransparentUnion(Ty);
1632
1633	// Check with the C++ ABI first.
1634	const RecordType *RT = Ty->getAs<RecordType>();
1635	if (RT) {
1636	CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1637	if (RAA == CGCXXABI::RAA_Indirect) {
1638	return getIndirectResult(Ty, false, State);
1639	} else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1640	// The field index doesn't matter, we'll fix it up later.
1641	return ABIArgInfo::getInAlloca(/FieldIndex=/0);
1642	}
1643	}
1644
1645	// Regcall uses the concept of a homogenous vector aggregate, similar
1646	// to other targets.
1647	const Type *Base = nullptr;
1648	uint64_t NumElts = 0;
1649	if (State.CC == llvm::CallingConv::X86_RegCall &&
1650	isHomogeneousAggregate(Ty, Base, NumElts)) {
1651
1652	if (State.FreeSSERegs >= NumElts) {
1653	State.FreeSSERegs -= NumElts;
1654	if (Ty->isBuiltinType() \|\| Ty->isVectorType())
1655	return ABIArgInfo::getDirect();
1656	return ABIArgInfo::getExpand();
1657	}
1658	return getIndirectResult(Ty, /ByVal=/false, State);
1659	}
1660
1661	if (isAggregateTypeForABI(Ty)) {
1662	// Structures with flexible arrays are always indirect.
1663	// FIXME: This should not be byval!
1664	if (RT && RT->getDecl()->hasFlexibleArrayMember())
1665	return getIndirectResult(Ty, true, State);
1666
1667	// Ignore empty structs/unions on non-Windows.
1668	if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1669	return ABIArgInfo::getIgnore();
1670
1671	llvm::LLVMContext &LLVMContext = getVMContext();
1672	llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1673	bool NeedsPadding = false;
1674	bool InReg;
1675	if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1676	unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1677	SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1678	llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1679	if (InReg)
1680	return ABIArgInfo::getDirectInReg(Result);
1681	else
1682	return ABIArgInfo::getDirect(Result);
1683	}
1684	llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1685
1686	// Expand small (<= 128-bit) record types when we know that the stack layout
1687	// of those arguments will match the struct. This is important because the
1688	// LLVM backend isn't smart enough to remove byval, which inhibits many
1689	// optimizations.
1690	// Don't do this for the MCU if there are still free integer registers
1691	// (see X86_64 ABI for full explanation).
1692	if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1693	(!IsMCUABI \|\| State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1694	return ABIArgInfo::getExpandWithPadding(
1695	State.CC == llvm::CallingConv::X86_FastCall \|\|
1696	State.CC == llvm::CallingConv::X86_VectorCall \|\|
1697	State.CC == llvm::CallingConv::X86_RegCall,
1698	PaddingType);
1699
1700	return getIndirectResult(Ty, true, State);
1701	}
1702
1703	if (const VectorType *VT = Ty->getAs<VectorType>()) {
1704	// On Darwin, some vectors are passed in memory, we handle this by passing
1705	// it as an i8/i16/i32/i64.
1706	if (IsDarwinVectorABI) {
1707	uint64_t Size = getContext().getTypeSize(Ty);
1708	if ((Size == 8 \|\| Size == 16 \|\| Size == 32) \|\|
1709	(Size == 64 && VT->getNumElements() == 1))
1710	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1711	Size));
1712	}
1713
1714	if (IsX86_MMXType(CGT.ConvertType(Ty)))
1715	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1716
1717	return ABIArgInfo::getDirect();
1718	}
1719
1720
1721	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1722	Ty = EnumTy->getDecl()->getIntegerType();
1723
1724	bool InReg = shouldPrimitiveUseInReg(Ty, State);
1725
1726	if (Ty->isPromotableIntegerType()) {
1727	if (InReg)
1728	return ABIArgInfo::getExtendInReg(Ty);
1729	return ABIArgInfo::getExtend(Ty);
1730	}
1731
1732	if (InReg)
1733	return ABIArgInfo::getDirectInReg();
1734	return ABIArgInfo::getDirect();
1735	}
1736
1737	void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1738	bool &UsedInAlloca) const {
1739	// Vectorcall x86 works subtly different than in x64, so the format is
1740	// a bit different than the x64 version. First, all vector types (not HVAs)
1741	// are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1742	// This differs from the x64 implementation, where the first 6 by INDEX get
1743	// registers.
1744	// After that, integers AND HVAs are assigned Left to Right in the same pass.
1745	// Integers are passed as ECX/EDX if one is available (in order). HVAs will
1746	// first take up the remaining YMM/XMM registers. If insufficient registers
1747	// remain but an integer register (ECX/EDX) is available, it will be passed
1748	// in that, else, on the stack.
1749	for (auto &I : FI.arguments()) {
1750	// First pass do all the vector types.
1751	const Type *Base = nullptr;
1752	uint64_t NumElts = 0;
1753	const QualType& Ty = I.type;
1754	if ((Ty->isVectorType() \|\| Ty->isBuiltinType()) &&
1755	isHomogeneousAggregate(Ty, Base, NumElts)) {
1756	if (State.FreeSSERegs >= NumElts) {
1757	State.FreeSSERegs -= NumElts;
1758	I.info = ABIArgInfo::getDirect();
1759	} else {
1760	I.info = classifyArgumentType(Ty, State);
1761	}
1762	UsedInAlloca \|= (I.info.getKind() == ABIArgInfo::InAlloca);
1763	}
1764	}
1765
1766	for (auto &I : FI.arguments()) {
1767	// Second pass, do the rest!
1768	const Type *Base = nullptr;
1769	uint64_t NumElts = 0;
1770	const QualType& Ty = I.type;
1771	bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1772
1773	if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1774	// Assign true HVAs (non vector/native FP types).
1775	if (State.FreeSSERegs >= NumElts) {
1776	State.FreeSSERegs -= NumElts;
1777	I.info = getDirectX86Hva();
1778	} else {
1779	I.info = getIndirectResult(Ty, /ByVal=/false, State);
1780	}
1781	} else if (!IsHva) {
1782	// Assign all Non-HVAs, so this will exclude Vector/FP args.
1783	I.info = classifyArgumentType(Ty, State);
1784	UsedInAlloca \|= (I.info.getKind() == ABIArgInfo::InAlloca);
1785	}
1786	}
1787	}
1788
1789	void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1790	CCState State(FI.getCallingConvention());
1791	if (IsMCUABI)
1792	State.FreeRegs = 3;
1793	else if (State.CC == llvm::CallingConv::X86_FastCall)
1794	State.FreeRegs = 2;
1795	else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1796	State.FreeRegs = 2;
1797	State.FreeSSERegs = 6;
1798	} else if (FI.getHasRegParm())
1799	State.FreeRegs = FI.getRegParm();
1800	else if (State.CC == llvm::CallingConv::X86_RegCall) {
1801	State.FreeRegs = 5;
1802	State.FreeSSERegs = 8;
1803	} else
1804	State.FreeRegs = DefaultNumRegisterParameters;
1805
1806	if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1807	FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1808	} else if (FI.getReturnInfo().isIndirect()) {
1809	// The C++ ABI is not aware of register usage, so we have to check if the
1810	// return value was sret and put it in a register ourselves if appropriate.
1811	if (State.FreeRegs) {
1812	--State.FreeRegs; // The sret parameter consumes a register.
1813	if (!IsMCUABI)
1814	FI.getReturnInfo().setInReg(true);
1815	}
1816	}
1817
1818	// The chain argument effectively gives us another free register.
1819	if (FI.isChainCall())
1820	++State.FreeRegs;
1821
1822	bool UsedInAlloca = false;
1823	if (State.CC == llvm::CallingConv::X86_VectorCall) {
1824	computeVectorCallArgs(FI, State, UsedInAlloca);
1825	} else {
1826	// If not vectorcall, revert to normal behavior.
1827	for (auto &I : FI.arguments()) {
1828	I.info = classifyArgumentType(I.type, State);
1829	UsedInAlloca \|= (I.info.getKind() == ABIArgInfo::InAlloca);
1830	}
1831	}
1832
1833	// If we needed to use inalloca for any argument, do a second pass and rewrite
1834	// all the memory arguments to use inalloca.
1835	if (UsedInAlloca)
1836	rewriteWithInAlloca(FI);
1837	}
1838
1839	void
1840	X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1841	CharUnits &StackOffset, ABIArgInfo &Info,
1842	QualType Type) const {
1843	// Arguments are always 4-byte-aligned.
1844	CharUnits FieldAlign = CharUnits::fromQuantity(4);
1845
1846	(0) . __assert_fail ("StackOffset.isMultipleOf(FieldAlign) && \"unaligned inalloca struct\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 1846, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1847	Info = ABIArgInfo::getInAlloca(FrameFields.size());
1848	FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1849	StackOffset += getContext().getTypeSizeInChars(Type);
1850
1851	// Insert padding bytes to respect alignment.
1852	CharUnits FieldEnd = StackOffset;
1853	StackOffset = FieldEnd.alignTo(FieldAlign);
1854	if (StackOffset != FieldEnd) {
1855	CharUnits NumBytes = StackOffset - FieldEnd;
1856	llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1857	Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1858	FrameFields.push_back(Ty);
1859	}
1860	}
1861
1862	static bool isArgInAlloca(const ABIArgInfo &Info) {
1863	// Leave ignored and inreg arguments alone.
1864	switch (Info.getKind()) {
1865	case ABIArgInfo::InAlloca:
1866	return true;
1867	case ABIArgInfo::Indirect:
1868	assert(Info.getIndirectByVal());
1869	return true;
1870	case ABIArgInfo::Ignore:
1871	return false;
1872	case ABIArgInfo::Direct:
1873	case ABIArgInfo::Extend:
1874	if (Info.getInReg())
1875	return false;
1876	return true;
1877	case ABIArgInfo::Expand:
1878	case ABIArgInfo::CoerceAndExpand:
1879	// These are aggregate types which are never passed in registers when
1880	// inalloca is involved.
1881	return true;
1882	}
1883	llvm_unreachable("invalid enum");
1884	}
1885
1886	void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1887	(0) . __assert_fail ("IsWin32StructABI && \"inalloca only supported on win32\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 1887, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(IsWin32StructABI && "inalloca only supported on win32");
1888
1889	// Build a packed struct type for all of the arguments in memory.
1890	SmallVector<llvm::Type *, 6> FrameFields;
1891
1892	// The stack alignment is always 4.
1893	CharUnits StackAlign = CharUnits::fromQuantity(4);
1894
1895	CharUnits StackOffset;
1896	CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1897
1898	// Put 'this' into the struct before 'sret', if necessary.
1899	bool IsThisCall =
1900	FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1901	ABIArgInfo &Ret = FI.getReturnInfo();
1902	if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1903	isArgInAlloca(I->info)) {
1904	addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1905	++I;
1906	}
1907
1908	// Put the sret parameter into the inalloca struct if it's in memory.
1909	if (Ret.isIndirect() && !Ret.getInReg()) {
1910	CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1911	addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1912	// On Windows, the hidden sret parameter is always returned in eax.
1913	Ret.setInAllocaSRet(IsWin32StructABI);
1914	}
1915
1916	// Skip the 'this' parameter in ecx.
1917	if (IsThisCall)
1918	++I;
1919
1920	// Put arguments passed in memory into the struct.
1921	for (; I != E; ++I) {
1922	if (isArgInAlloca(I->info))
1923	addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1924	}
1925
1926	FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1927	/isPacked=/true),
1928	StackAlign);
1929	}
1930
1931	Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1932	Address VAListAddr, QualType Ty) const {
1933
1934	auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1935
1936	// x86-32 changes the alignment of certain arguments on the stack.
1937	//
1938	// Just messing with TypeInfo like this works because we never pass
1939	// anything indirectly.
1940	TypeInfo.second = CharUnits::fromQuantity(
1941	getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1942
1943	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /Indirect/ false,
1944	TypeInfo, CharUnits::fromQuantity(4),
1945	/AllowHigherAlign/ true);
1946	}
1947
1948	bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1949	const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1950	assert(Triple.getArch() == llvm::Triple::x86);
1951
1952	switch (Opts.getStructReturnConvention()) {
1953	case CodeGenOptions::SRCK_Default:
1954	break;
1955	case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1956	return false;
1957	case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1958	return true;
1959	}
1960
1961	if (Triple.isOSDarwin() \|\| Triple.isOSIAMCU())
1962	return true;
1963
1964	switch (Triple.getOS()) {
1965	case llvm::Triple::DragonFly:
1966	case llvm::Triple::FreeBSD:
1967	case llvm::Triple::OpenBSD:
1968	case llvm::Triple::Win32:
1969	return true;
1970	default:
1971	return false;
1972	}
1973	}
1974
1975	void X86_32TargetCodeGenInfo::setTargetAttributes(
1976	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &CGM) const {
1977	if (GV->isDeclaration())
1978	return;
1979	if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1980	if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1981	llvm::Function *Fn = cast<llvm::Function>(GV);
1982	Fn->addFnAttr("stackrealign");
1983	}
1984	if (FD->hasAttr<AnyX86InterruptAttr>()) {
1985	llvm::Function *Fn = cast<llvm::Function>(GV);
1986	Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1987	}
1988	}
1989	}
1990
1991	bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1992	CodeGen::CodeGenFunction &CGF,
1993	llvm::Value *Address) const {
1994	CodeGen::CGBuilderTy &Builder = CGF.Builder;
1995
1996	llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1997
1998	// 0-7 are the eight integer registers; the order is different
1999	// on Darwin (for EH), but the range is the same.
2000	// 8 is %eip.
2001	AssignToArrayRange(Builder, Address, Four8, 0, 8);
2002
2003	if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2004	// 12-16 are st(0..4). Not sure why we stop at 4.
2005	// These have size 16, which is sizeof(long double) on
2006	// platforms with 8-byte alignment for that type.
2007	llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2008	AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2009
2010	} else {
2011	// 9 is %eflags, which doesn't get a size on Darwin for some
2012	// reason.
2013	Builder.CreateAlignedStore(
2014	Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2015	CharUnits::One());
2016
2017	// 11-16 are st(0..5). Not sure why we stop at 5.
2018	// These have size 12, which is sizeof(long double) on
2019	// platforms with 4-byte alignment for that type.
2020	llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2021	AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2022	}
2023
2024	return false;
2025	}
2026
2027	//===----------------------------------------------------------------------===//
2028	// X86-64 ABI Implementation
2029	//===----------------------------------------------------------------------===//
2030
2031
2032	namespace {
2033	/// The AVX ABI level for X86 targets.
2034	enum class X86AVXABILevel {
2035	None,
2036	AVX,
2037	AVX512
2038	};
2039
2040	/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2041	static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2042	switch (AVXLevel) {
2043	case X86AVXABILevel::AVX512:
2044	return 512;
2045	case X86AVXABILevel::AVX:
2046	return 256;
2047	case X86AVXABILevel::None:
2048	return 128;
2049	}
2050	llvm_unreachable("Unknown AVXLevel");
2051	}
2052
2053	/// X86_64ABIInfo - The X86_64 ABI information.
2054	class X86_64ABIInfo : public SwiftABIInfo {
2055	enum Class {
2056	Integer = 0,
2057	SSE,
2058	SSEUp,
2059	X87,
2060	X87Up,
2061	ComplexX87,
2062	NoClass,
2063	Memory
2064	};
2065
2066	/// merge - Implement the X86_64 ABI merging algorithm.
2067	///
2068	/// Merge an accumulating classification \arg Accum with a field
2069	/// classification \arg Field.
2070	///
2071	/// \param Accum - The accumulating classification. This should
2072	/// always be either NoClass or the result of a previous merge
2073	/// call. In addition, this should never be Memory (the caller
2074	/// should just return Memory for the aggregate).
2075	static Class merge(Class Accum, Class Field);
2076
2077	/// postMerge - Implement the X86_64 ABI post merging algorithm.
2078	///
2079	/// Post merger cleanup, reduces a malformed Hi and Lo pair to
2080	/// final MEMORY or SSE classes when necessary.
2081	///
2082	/// \param AggregateSize - The size of the current aggregate in
2083	/// the classification process.
2084	///
2085	/// \param Lo - The classification for the parts of the type
2086	/// residing in the low word of the containing object.
2087	///
2088	/// \param Hi - The classification for the parts of the type
2089	/// residing in the higher words of the containing object.
2090	///
2091	void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2092
2093	/// classify - Determine the x86_64 register classes in which the
2094	/// given type T should be passed.
2095	///
2096	/// \param Lo - The classification for the parts of the type
2097	/// residing in the low word of the containing object.
2098	///
2099	/// \param Hi - The classification for the parts of the type
2100	/// residing in the high word of the containing object.
2101	///
2102	/// \param OffsetBase - The bit offset of this type in the
2103	/// containing object. Some parameters are classified different
2104	/// depending on whether they straddle an eightbyte boundary.
2105	///
2106	/// \param isNamedArg - Whether the argument in question is a "named"
2107	/// argument, as used in AMD64-ABI 3.5.7.
2108	///
2109	/// If a word is unused its result will be NoClass; if a type should
2110	/// be passed in Memory then at least the classification of \arg Lo
2111	/// will be Memory.
2112	///
2113	/// The \arg Lo class will be NoClass iff the argument is ignored.
2114	///
2115	/// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2116	/// also be ComplexX87.
2117	void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2118	bool isNamedArg) const;
2119
2120	llvm::Type *GetByteVectorType(QualType Ty) const;
2121	llvm::Type GetSSETypeAtOffset(llvm::Type IRType,
2122	unsigned IROffset, QualType SourceTy,
2123	unsigned SourceOffset) const;
2124	llvm::Type GetINTEGERTypeAtOffset(llvm::Type IRType,
2125	unsigned IROffset, QualType SourceTy,
2126	unsigned SourceOffset) const;
2127
2128	/// getIndirectResult - Give a source type \arg Ty, return a suitable result
2129	/// such that the argument will be returned in memory.
2130	ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2131
2132	/// getIndirectResult - Give a source type \arg Ty, return a suitable result
2133	/// such that the argument will be passed in memory.
2134	///
2135	/// \param freeIntRegs - The number of free integer registers remaining
2136	/// available.
2137	ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2138
2139	ABIArgInfo classifyReturnType(QualType RetTy) const;
2140
2141	ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2142	unsigned &neededInt, unsigned &neededSSE,
2143	bool isNamedArg) const;
2144
2145	ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2146	unsigned &NeededSSE) const;
2147
2148	ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2149	unsigned &NeededSSE) const;
2150
2151	bool IsIllegalVectorType(QualType Ty) const;
2152
2153	/// The 0.98 ABI revision clarified a lot of ambiguities,
2154	/// unfortunately in ways that were not always consistent with
2155	/// certain previous compilers. In particular, platforms which
2156	/// required strict binary compatibility with older versions of GCC
2157	/// may need to exempt themselves.
2158	bool honorsRevision0_98() const {
2159	return !getTarget().getTriple().isOSDarwin();
2160	}
2161
2162	/// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2163	/// classify it as INTEGER (for compatibility with older clang compilers).
2164	bool classifyIntegerMMXAsSSE() const {
2165	// Clang <= 3.8 did not do this.
2166	if (getContext().getLangOpts().getClangABICompat() <=
2167	LangOptions::ClangABI::Ver3_8)
2168	return false;
2169
2170	const llvm::Triple &Triple = getTarget().getTriple();
2171	if (Triple.isOSDarwin() \|\| Triple.getOS() == llvm::Triple::PS4)
2172	return false;
2173	if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2174	return false;
2175	return true;
2176	}
2177
2178	X86AVXABILevel AVXLevel;
2179	// Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2180	// 64-bit hardware.
2181	bool Has64BitPointers;
2182
2183	public:
2184	X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2185	SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2186	Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2187	}
2188
2189	bool isPassedUsingAVXType(QualType type) const {
2190	unsigned neededInt, neededSSE;
2191	// The freeIntRegs argument doesn't matter here.
2192	ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2193	/isNamedArg/true);
2194	if (info.isDirect()) {
2195	llvm::Type *ty = info.getCoerceToType();
2196	if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2197	return (vectorTy->getBitWidth() > 128);
2198	}
2199	return false;
2200	}
2201
2202	void computeInfo(CGFunctionInfo &FI) const override;
2203
2204	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2205	QualType Ty) const override;
2206	Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2207	QualType Ty) const override;
2208
2209	bool has64BitPointers() const {
2210	return Has64BitPointers;
2211	}
2212
2213	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2214	bool asReturnValue) const override {
2215	return occupiesMoreThan(CGT, scalars, /total/ 4);
2216	}
2217	bool isSwiftErrorInRegister() const override {
2218	return true;
2219	}
2220	};
2221
2222	/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2223	class WinX86_64ABIInfo : public SwiftABIInfo {
2224	public:
2225	WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2226	: SwiftABIInfo(CGT),
2227	IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2228
2229	void computeInfo(CGFunctionInfo &FI) const override;
2230
2231	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2232	QualType Ty) const override;
2233
2234	bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2235	// FIXME: Assumes vectorcall is in use.
2236	return isX86VectorTypeForVectorCall(getContext(), Ty);
2237	}
2238
2239	bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2240	uint64_t NumMembers) const override {
2241	// FIXME: Assumes vectorcall is in use.
2242	return isX86VectorCallAggregateSmallEnough(NumMembers);
2243	}
2244
2245	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2246	bool asReturnValue) const override {
2247	return occupiesMoreThan(CGT, scalars, /total/ 4);
2248	}
2249
2250	bool isSwiftErrorInRegister() const override {
2251	return true;
2252	}
2253
2254	private:
2255	ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2256	bool IsVectorCall, bool IsRegCall) const;
2257	ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2258	const ABIArgInfo &current) const;
2259	void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2260	bool IsVectorCall, bool IsRegCall) const;
2261
2262	bool IsMingw64;
2263	};
2264
2265	class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2266	public:
2267	X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2268	: TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2269
2270	const X86_64ABIInfo &getABIInfo() const {
2271	return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2272	}
2273
2274	/// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2275	/// the autoreleaseRV/retainRV optimization.
2276	bool shouldSuppressTailCallsOfRetainAutoreleasedReturnValue() const override {
2277	return true;
2278	}
2279
2280	int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2281	return 7;
2282	}
2283
2284	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2285	llvm::Value *Address) const override {
2286	llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2287
2288	// 0-15 are the 16 integer registers.
2289	// 16 is %rip.
2290	AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2291	return false;
2292	}
2293
2294	llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2295	StringRef Constraint,
2296	llvm::Type* Ty) const override {
2297	return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2298	}
2299
2300	bool isNoProtoCallVariadic(const CallArgList &args,
2301	const FunctionNoProtoType *fnType) const override {
2302	// The default CC on x86-64 sets %al to the number of SSA
2303	// registers used, and GCC sets this when calling an unprototyped
2304	// function, so we override the default behavior. However, don't do
2305	// that when AVX types are involved: the ABI explicitly states it is
2306	// undefined, and it doesn't work in practice because of how the ABI
2307	// defines varargs anyway.
2308	if (fnType->getCallConv() == CC_C) {
2309	bool HasAVXType = false;
2310	for (CallArgList::const_iterator
2311	it = args.begin(), ie = args.end(); it != ie; ++it) {
2312	if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2313	HasAVXType = true;
2314	break;
2315	}
2316	}
2317
2318	if (!HasAVXType)
2319	return true;
2320	}
2321
2322	return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2323	}
2324
2325	llvm::Constant *
2326	getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2327	unsigned Sig = (0xeb << 0) \| // jmp rel8
2328	(0x06 << 8) \| // .+0x08
2329	('v' << 16) \|
2330	('2' << 24);
2331	return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2332	}
2333
2334	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
2335	CodeGen::CodeGenModule &CGM) const override {
2336	if (GV->isDeclaration())
2337	return;
2338	if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2339	if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2340	llvm::Function *Fn = cast<llvm::Function>(GV);
2341	Fn->addFnAttr("stackrealign");
2342	}
2343	if (FD->hasAttr<AnyX86InterruptAttr>()) {
2344	llvm::Function *Fn = cast<llvm::Function>(GV);
2345	Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2346	}
2347	}
2348	}
2349	};
2350
2351	class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2352	public:
2353	PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2354	: X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2355
2356	void getDependentLibraryOption(llvm::StringRef Lib,
2357	llvm::SmallString<24> &Opt) const override {
2358	Opt = "\01";
2359	// If the argument contains a space, enclose it in quotes.
2360	if (Lib.find(" ") != StringRef::npos)
2361	Opt += "\"" + Lib.str() + "\"";
2362	else
2363	Opt += Lib;
2364	}
2365	};
2366
2367	static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2368	// If the argument does not end in .lib, automatically add the suffix.
2369	// If the argument contains a space, enclose it in quotes.
2370	// This matches the behavior of MSVC.
2371	bool Quote = (Lib.find(" ") != StringRef::npos);
2372	std::string ArgStr = Quote ? "\"" : "";
2373	ArgStr += Lib;
2374	if (!Lib.endswith_lower(".lib") && !Lib.endswith_lower(".a"))
2375	ArgStr += ".lib";
2376	ArgStr += Quote ? "\"" : "";
2377	return ArgStr;
2378	}
2379
2380	class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2381	public:
2382	WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2383	bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2384	unsigned NumRegisterParameters)
2385	: X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2386	Win32StructABI, NumRegisterParameters, false) {}
2387
2388	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
2389	CodeGen::CodeGenModule &CGM) const override;
2390
2391	void getDependentLibraryOption(llvm::StringRef Lib,
2392	llvm::SmallString<24> &Opt) const override {
2393	Opt = "/DEFAULTLIB:";
2394	Opt += qualifyWindowsLibrary(Lib);
2395	}
2396
2397	void getDetectMismatchOption(llvm::StringRef Name,
2398	llvm::StringRef Value,
2399	llvm::SmallString<32> &Opt) const override {
2400	Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2401	}
2402	};
2403
2404	static void addStackProbeTargetAttributes(const Decl D, llvm::GlobalValue GV,
2405	CodeGen::CodeGenModule &CGM) {
2406	if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2407
2408	if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2409	Fn->addFnAttr("stack-probe-size",
2410	llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2411	if (CGM.getCodeGenOpts().NoStackArgProbe)
2412	Fn->addFnAttr("no-stack-arg-probe");
2413	}
2414	}
2415
2416	void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2417	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &CGM) const {
2418	X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2419	if (GV->isDeclaration())
2420	return;
2421	addStackProbeTargetAttributes(D, GV, CGM);
2422	}
2423
2424	class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2425	public:
2426	WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2427	X86AVXABILevel AVXLevel)
2428	: TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2429
2430	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
2431	CodeGen::CodeGenModule &CGM) const override;
2432
2433	int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2434	return 7;
2435	}
2436
2437	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2438	llvm::Value *Address) const override {
2439	llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2440
2441	// 0-15 are the 16 integer registers.
2442	// 16 is %rip.
2443	AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2444	return false;
2445	}
2446
2447	void getDependentLibraryOption(llvm::StringRef Lib,
2448	llvm::SmallString<24> &Opt) const override {
2449	Opt = "/DEFAULTLIB:";
2450	Opt += qualifyWindowsLibrary(Lib);
2451	}
2452
2453	void getDetectMismatchOption(llvm::StringRef Name,
2454	llvm::StringRef Value,
2455	llvm::SmallString<32> &Opt) const override {
2456	Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2457	}
2458	};
2459
2460	void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2461	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &CGM) const {
2462	TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2463	if (GV->isDeclaration())
2464	return;
2465	if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2466	if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2467	llvm::Function *Fn = cast<llvm::Function>(GV);
2468	Fn->addFnAttr("stackrealign");
2469	}
2470	if (FD->hasAttr<AnyX86InterruptAttr>()) {
2471	llvm::Function *Fn = cast<llvm::Function>(GV);
2472	Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2473	}
2474	}
2475
2476	addStackProbeTargetAttributes(D, GV, CGM);
2477	}
2478	}
2479
2480	void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2481	Class &Hi) const {
2482	// AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2483	//
2484	// (a) If one of the classes is Memory, the whole argument is passed in
2485	// memory.
2486	//
2487	// (b) If X87UP is not preceded by X87, the whole argument is passed in
2488	// memory.
2489	//
2490	// (c) If the size of the aggregate exceeds two eightbytes and the first
2491	// eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2492	// argument is passed in memory. NOTE: This is necessary to keep the
2493	// ABI working for processors that don't support the __m256 type.
2494	//
2495	// (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2496	//
2497	// Some of these are enforced by the merging logic. Others can arise
2498	// only with unions; for example:
2499	// union { _Complex double; unsigned; }
2500	//
2501	// Note that clauses (b) and (c) were added in 0.98.
2502	//
2503	if (Hi == Memory)
2504	Lo = Memory;
2505	if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2506	Lo = Memory;
2507	if (AggregateSize > 128 && (Lo != SSE \|\| Hi != SSEUp))
2508	Lo = Memory;
2509	if (Hi == SSEUp && Lo != SSE)
2510	Hi = SSE;
2511	}
2512
2513	X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2514	// AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2515	// classified recursively so that always two fields are
2516	// considered. The resulting class is calculated according to
2517	// the classes of the fields in the eightbyte:
2518	//
2519	// (a) If both classes are equal, this is the resulting class.
2520	//
2521	// (b) If one of the classes is NO_CLASS, the resulting class is
2522	// the other class.
2523	//
2524	// (c) If one of the classes is MEMORY, the result is the MEMORY
2525	// class.
2526	//
2527	// (d) If one of the classes is INTEGER, the result is the
2528	// INTEGER.
2529	//
2530	// (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2531	// MEMORY is used as class.
2532	//
2533	// (f) Otherwise class SSE is used.
2534
2535	// Accum should never be memory (we should have returned) or
2536	// ComplexX87 (because this cannot be passed in a structure).
2537	(0) . __assert_fail ("(Accum != Memory && Accum != ComplexX87) && \"Invalid accumulated classification during merge.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2538, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Accum != Memory && Accum != ComplexX87) &&
2538	(0) . __assert_fail ("(Accum != Memory && Accum != ComplexX87) && \"Invalid accumulated classification during merge.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2538, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Invalid accumulated classification during merge.");
2539	if (Accum == Field \|\| Field == NoClass)
2540	return Accum;
2541	if (Field == Memory)
2542	return Memory;
2543	if (Accum == NoClass)
2544	return Field;
2545	if (Accum == Integer \|\| Field == Integer)
2546	return Integer;
2547	if (Field == X87 \|\| Field == X87Up \|\| Field == ComplexX87 \|\|
2548	Accum == X87 \|\| Accum == X87Up)
2549	return Memory;
2550	return SSE;
2551	}
2552
2553	void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2554	Class &Lo, Class &Hi, bool isNamedArg) const {
2555	// FIXME: This code can be simplified by introducing a simple value class for
2556	// Class pairs with appropriate constructor methods for the various
2557	// situations.
2558
2559	// FIXME: Some of the split computations are wrong; unaligned vectors
2560	// shouldn't be passed in registers for example, so there is no chance they
2561	// can straddle an eightbyte. Verify & simplify.
2562
2563	Lo = Hi = NoClass;
2564
2565	Class &Current = OffsetBase < 64 ? Lo : Hi;
2566	Current = Memory;
2567
2568	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2569	BuiltinType::Kind k = BT->getKind();
2570
2571	if (k == BuiltinType::Void) {
2572	Current = NoClass;
2573	} else if (k == BuiltinType::Int128 \|\| k == BuiltinType::UInt128) {
2574	Lo = Integer;
2575	Hi = Integer;
2576	} else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2577	Current = Integer;
2578	} else if (k == BuiltinType::Float \|\| k == BuiltinType::Double) {
2579	Current = SSE;
2580	} else if (k == BuiltinType::LongDouble) {
2581	const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2582	if (LDF == &llvm::APFloat::IEEEquad()) {
2583	Lo = SSE;
2584	Hi = SSEUp;
2585	} else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2586	Lo = X87;
2587	Hi = X87Up;
2588	} else if (LDF == &llvm::APFloat::IEEEdouble()) {
2589	Current = SSE;
2590	} else
2591	llvm_unreachable("unexpected long double representation!");
2592	}
2593	// FIXME: _Decimal32 and _Decimal64 are SSE.
2594	// FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2595	return;
2596	}
2597
2598	if (const EnumType *ET = Ty->getAs<EnumType>()) {
2599	// Classify the underlying integer type.
2600	classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2601	return;
2602	}
2603
2604	if (Ty->hasPointerRepresentation()) {
2605	Current = Integer;
2606	return;
2607	}
2608
2609	if (Ty->isMemberPointerType()) {
2610	if (Ty->isMemberFunctionPointerType()) {
2611	if (Has64BitPointers) {
2612	// If Has64BitPointers, this is an {i64, i64}, so classify both
2613	// Lo and Hi now.
2614	Lo = Hi = Integer;
2615	} else {
2616	// Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2617	// straddles an eightbyte boundary, Hi should be classified as well.
2618	uint64_t EB_FuncPtr = (OffsetBase) / 64;
2619	uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2620	if (EB_FuncPtr != EB_ThisAdj) {
2621	Lo = Hi = Integer;
2622	} else {
2623	Current = Integer;
2624	}
2625	}
2626	} else {
2627	Current = Integer;
2628	}
2629	return;
2630	}
2631
2632	if (const VectorType *VT = Ty->getAs<VectorType>()) {
2633	uint64_t Size = getContext().getTypeSize(VT);
2634	if (Size == 1 \|\| Size == 8 \|\| Size == 16 \|\| Size == 32) {
2635	// gcc passes the following as integer:
2636	// 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2637	// 2 bytes - <2 x char>, <1 x short>
2638	// 1 byte - <1 x char>
2639	Current = Integer;
2640
2641	// If this type crosses an eightbyte boundary, it should be
2642	// split.
2643	uint64_t EB_Lo = (OffsetBase) / 64;
2644	uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2645	if (EB_Lo != EB_Hi)
2646	Hi = Lo;
2647	} else if (Size == 64) {
2648	QualType ElementType = VT->getElementType();
2649
2650	// gcc passes <1 x double> in memory. :(
2651	if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2652	return;
2653
2654	// gcc passes <1 x long long> as SSE but clang used to unconditionally
2655	// pass them as integer. For platforms where clang is the de facto
2656	// platform compiler, we must continue to use integer.
2657	if (!classifyIntegerMMXAsSSE() &&
2658	(ElementType->isSpecificBuiltinType(BuiltinType::LongLong) \|\|
2659	ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) \|\|
2660	ElementType->isSpecificBuiltinType(BuiltinType::Long) \|\|
2661	ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2662	Current = Integer;
2663	else
2664	Current = SSE;
2665
2666	// If this type crosses an eightbyte boundary, it should be
2667	// split.
2668	if (OffsetBase && OffsetBase != 64)
2669	Hi = Lo;
2670	} else if (Size == 128 \|\|
2671	(isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2672	// Arguments of 256-bits are split into four eightbyte chunks. The
2673	// least significant one belongs to class SSE and all the others to class
2674	// SSEUP. The original Lo and Hi design considers that types can't be
2675	// greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2676	// This design isn't correct for 256-bits, but since there're no cases
2677	// where the upper parts would need to be inspected, avoid adding
2678	// complexity and just consider Hi to match the 64-256 part.
2679	//
2680	// Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2681	// registers if they are "named", i.e. not part of the "..." of a
2682	// variadic function.
2683	//
2684	// Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2685	// split into eight eightbyte chunks, one SSE and seven SSEUP.
2686	Lo = SSE;
2687	Hi = SSEUp;
2688	}
2689	return;
2690	}
2691
2692	if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2693	QualType ET = getContext().getCanonicalType(CT->getElementType());
2694
2695	uint64_t Size = getContext().getTypeSize(Ty);
2696	if (ET->isIntegralOrEnumerationType()) {
2697	if (Size <= 64)
2698	Current = Integer;
2699	else if (Size <= 128)
2700	Lo = Hi = Integer;
2701	} else if (ET == getContext().FloatTy) {
2702	Current = SSE;
2703	} else if (ET == getContext().DoubleTy) {
2704	Lo = Hi = SSE;
2705	} else if (ET == getContext().LongDoubleTy) {
2706	const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2707	if (LDF == &llvm::APFloat::IEEEquad())
2708	Current = Memory;
2709	else if (LDF == &llvm::APFloat::x87DoubleExtended())
2710	Current = ComplexX87;
2711	else if (LDF == &llvm::APFloat::IEEEdouble())
2712	Lo = Hi = SSE;
2713	else
2714	llvm_unreachable("unexpected long double representation!");
2715	}
2716
2717	// If this complex type crosses an eightbyte boundary then it
2718	// should be split.
2719	uint64_t EB_Real = (OffsetBase) / 64;
2720	uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2721	if (Hi == NoClass && EB_Real != EB_Imag)
2722	Hi = Lo;
2723
2724	return;
2725	}
2726
2727	if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2728	// Arrays are treated like structures.
2729
2730	uint64_t Size = getContext().getTypeSize(Ty);
2731
2732	// AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2733	// than eight eightbytes, ..., it has class MEMORY.
2734	if (Size > 512)
2735	return;
2736
2737	// AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2738	// fields, it has class MEMORY.
2739	//
2740	// Only need to check alignment of array base.
2741	if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2742	return;
2743
2744	// Otherwise implement simplified merge. We could be smarter about
2745	// this, but it isn't worth it and would be harder to verify.
2746	Current = NoClass;
2747	uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2748	uint64_t ArraySize = AT->getSize().getZExtValue();
2749
2750	// The only case a 256-bit wide vector could be used is when the array
2751	// contains a single 256-bit element. Since Lo and Hi logic isn't extended
2752	// to work for sizes wider than 128, early check and fallback to memory.
2753	//
2754	if (Size > 128 &&
2755	(Size != EltSize \|\| Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2756	return;
2757
2758	for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2759	Class FieldLo, FieldHi;
2760	classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2761	Lo = merge(Lo, FieldLo);
2762	Hi = merge(Hi, FieldHi);
2763	if (Lo == Memory \|\| Hi == Memory)
2764	break;
2765	}
2766
2767	postMerge(Size, Lo, Hi);
2768	(0) . __assert_fail ("(Hi != SSEUp \|\| Lo == SSE) && \"Invalid SSEUp array classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2768, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi != SSEUp \|\| Lo == SSE) && "Invalid SSEUp array classification.");
2769	return;
2770	}
2771
2772	if (const RecordType *RT = Ty->getAs<RecordType>()) {
2773	uint64_t Size = getContext().getTypeSize(Ty);
2774
2775	// AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2776	// than eight eightbytes, ..., it has class MEMORY.
2777	if (Size > 512)
2778	return;
2779
2780	// AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2781	// copy constructor or a non-trivial destructor, it is passed by invisible
2782	// reference.
2783	if (getRecordArgABI(RT, getCXXABI()))
2784	return;
2785
2786	const RecordDecl *RD = RT->getDecl();
2787
2788	// Assume variable sized types are passed in memory.
2789	if (RD->hasFlexibleArrayMember())
2790	return;
2791
2792	const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2793
2794	// Reset Lo class, this will be recomputed.
2795	Current = NoClass;
2796
2797	// If this is a C++ record, classify the bases first.
2798	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2799	for (const auto &I : CXXRD->bases()) {
2800	(0) . __assert_fail ("!I.isVirtual() && !I.getType()->isDependentType() && \"Unexpected base class!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2801, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2801	(0) . __assert_fail ("!I.isVirtual() && !I.getType()->isDependentType() && \"Unexpected base class!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2801, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected base class!");
2802	const CXXRecordDecl *Base =
2803	cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2804
2805	// Classify this field.
2806	//
2807	// AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2808	// single eightbyte, each is classified separately. Each eightbyte gets
2809	// initialized to class NO_CLASS.
2810	Class FieldLo, FieldHi;
2811	uint64_t Offset =
2812	OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2813	classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2814	Lo = merge(Lo, FieldLo);
2815	Hi = merge(Hi, FieldHi);
2816	if (Lo == Memory \|\| Hi == Memory) {
2817	postMerge(Size, Lo, Hi);
2818	return;
2819	}
2820	}
2821	}
2822
2823	// Classify the fields one at a time, merging the results.
2824	unsigned idx = 0;
2825	for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2826	i != e; ++i, ++idx) {
2827	uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2828	bool BitField = i->isBitField();
2829
2830	// Ignore padding bit-fields.
2831	if (BitField && i->isUnnamedBitfield())
2832	continue;
2833
2834	// AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2835	// four eightbytes, or it contains unaligned fields, it has class MEMORY.
2836	//
2837	// The only case a 256-bit wide vector could be used is when the struct
2838	// contains a single 256-bit element. Since Lo and Hi logic isn't extended
2839	// to work for sizes wider than 128, early check and fallback to memory.
2840	//
2841	if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) \|\|
2842	Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2843	Lo = Memory;
2844	postMerge(Size, Lo, Hi);
2845	return;
2846	}
2847	// Note, skip this test for bit-fields, see below.
2848	if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2849	Lo = Memory;
2850	postMerge(Size, Lo, Hi);
2851	return;
2852	}
2853
2854	// Classify this field.
2855	//
2856	// AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2857	// exceeds a single eightbyte, each is classified
2858	// separately. Each eightbyte gets initialized to class
2859	// NO_CLASS.
2860	Class FieldLo, FieldHi;
2861
2862	// Bit-fields require special handling, they do not force the
2863	// structure to be passed in memory even if unaligned, and
2864	// therefore they can straddle an eightbyte.
2865	if (BitField) {
2866	isUnnamedBitfield()", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2866, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!i->isUnnamedBitfield());
2867	uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2868	uint64_t Size = i->getBitWidthValue(getContext());
2869
2870	uint64_t EB_Lo = Offset / 64;
2871	uint64_t EB_Hi = (Offset + Size - 1) / 64;
2872
2873	if (EB_Lo) {
2874	16 bytes.") ? static_cast (0) . __assert_fail ("EB_Hi == EB_Lo && \"Invalid classification, type > 16 bytes.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2874, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2875	FieldLo = NoClass;
2876	FieldHi = Integer;
2877	} else {
2878	FieldLo = Integer;
2879	FieldHi = EB_Hi ? Integer : NoClass;
2880	}
2881	} else
2882	classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2883	Lo = merge(Lo, FieldLo);
2884	Hi = merge(Hi, FieldHi);
2885	if (Lo == Memory \|\| Hi == Memory)
2886	break;
2887	}
2888
2889	postMerge(Size, Lo, Hi);
2890	}
2891	}
2892
2893	ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2894	// If this is a scalar LLVM value then assume LLVM will pass it in the right
2895	// place naturally.
2896	if (!isAggregateTypeForABI(Ty)) {
2897	// Treat an enum type as its underlying type.
2898	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2899	Ty = EnumTy->getDecl()->getIntegerType();
2900
2901	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
2902	: ABIArgInfo::getDirect());
2903	}
2904
2905	return getNaturalAlignIndirect(Ty);
2906	}
2907
2908	bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2909	if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2910	uint64_t Size = getContext().getTypeSize(VecTy);
2911	unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2912	if (Size <= 64 \|\| Size > LargestVector)
2913	return true;
2914	}
2915
2916	return false;
2917	}
2918
2919	ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2920	unsigned freeIntRegs) const {
2921	// If this is a scalar LLVM value then assume LLVM will pass it in the right
2922	// place naturally.
2923	//
2924	// This assumption is optimistic, as there could be free registers available
2925	// when we need to pass this argument in memory, and LLVM could try to pass
2926	// the argument in the free register. This does not seem to happen currently,
2927	// but this code would be much safer if we could mark the argument with
2928	// 'onstack'. See PR12193.
2929	if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2930	// Treat an enum type as its underlying type.
2931	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2932	Ty = EnumTy->getDecl()->getIntegerType();
2933
2934	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
2935	: ABIArgInfo::getDirect());
2936	}
2937
2938	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2939	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2940
2941	// Compute the byval alignment. We specify the alignment of the byval in all
2942	// cases so that the mid-level optimizer knows the alignment of the byval.
2943	unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2944
2945	// Attempt to avoid passing indirect results using byval when possible. This
2946	// is important for good codegen.
2947	//
2948	// We do this by coercing the value into a scalar type which the backend can
2949	// handle naturally (i.e., without using byval).
2950	//
2951	// For simplicity, we currently only do this when we have exhausted all of the
2952	// free integer registers. Doing this when there are free integer registers
2953	// would require more care, as we would have to ensure that the coerced value
2954	// did not claim the unused register. That would require either reording the
2955	// arguments to the function (so that any subsequent inreg values came first),
2956	// or only doing this optimization when there were no following arguments that
2957	// might be inreg.
2958	//
2959	// We currently expect it to be rare (particularly in well written code) for
2960	// arguments to be passed on the stack when there are still free integer
2961	// registers available (this would typically imply large structs being passed
2962	// by value), so this seems like a fair tradeoff for now.
2963	//
2964	// We can revisit this if the backend grows support for 'onstack' parameter
2965	// attributes. See PR12193.
2966	if (freeIntRegs == 0) {
2967	uint64_t Size = getContext().getTypeSize(Ty);
2968
2969	// If this type fits in an eightbyte, coerce it into the matching integral
2970	// type, which will end up on the stack (with alignment 8).
2971	if (Align == 8 && Size <= 64)
2972	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2973	Size));
2974	}
2975
2976	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
2977	}
2978
2979	/// The ABI specifies that a value should be passed in a full vector XMM/YMM
2980	/// register. Pick an LLVM IR type that will be passed as a vector register.
2981	llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2982	// Wrapper structs/arrays that only contain vectors are passed just like
2983	// vectors; strip them off if present.
2984	if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2985	Ty = QualType(InnerTy, 0);
2986
2987	llvm::Type *IRType = CGT.ConvertType(Ty);
2988	if (isa<llvm::VectorType>(IRType) \|\|
2989	IRType->getTypeID() == llvm::Type::FP128TyID)
2990	return IRType;
2991
2992	// We couldn't find the preferred IR vector type for 'Ty'.
2993	uint64_t Size = getContext().getTypeSize(Ty);
2994	(0) . __assert_fail ("(Size == 128 \|\| Size == 256 \|\| Size == 512) && \"Invalid type found!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 2994, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Size == 128 \|\| Size == 256 \|\| Size == 512) && "Invalid type found!");
2995
2996	// Return a LLVM IR vector type based on the size of 'Ty'.
2997	return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2998	Size / 64);
2999	}
3000
3001	/// BitsContainNoUserData - Return true if the specified [start,end) bit range
3002	/// is known to either be off the end of the specified type or being in
3003	/// alignment padding. The user type specified is known to be at most 128 bits
3004	/// in size, and have passed through X86_64ABIInfo::classify with a successful
3005	/// classification that put one of the two halves in the INTEGER class.
3006	///
3007	/// It is conservatively correct to return false.
3008	static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
3009	unsigned EndBit, ASTContext &Context) {
3010	// If the bytes being queried are off the end of the type, there is no user
3011	// data hiding here. This handles analysis of builtins, vectors and other
3012	// types that don't contain interesting padding.
3013	unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3014	if (TySize <= StartBit)
3015	return true;
3016
3017	if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3018	unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3019	unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3020
3021	// Check each element to see if the element overlaps with the queried range.
3022	for (unsigned i = 0; i != NumElts; ++i) {
3023	// If the element is after the span we care about, then we're done..
3024	unsigned EltOffset = i*EltSize;
3025	if (EltOffset >= EndBit) break;
3026
3027	unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
3028	if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3029	EndBit-EltOffset, Context))
3030	return false;
3031	}
3032	// If it overlaps no elements, then it is safe to process as padding.
3033	return true;
3034	}
3035
3036	if (const RecordType *RT = Ty->getAs<RecordType>()) {
3037	const RecordDecl *RD = RT->getDecl();
3038	const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3039
3040	// If this is a C++ record, check the bases first.
3041	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3042	for (const auto &I : CXXRD->bases()) {
3043	(0) . __assert_fail ("!I.isVirtual() && !I.getType()->isDependentType() && \"Unexpected base class!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3044, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3044	(0) . __assert_fail ("!I.isVirtual() && !I.getType()->isDependentType() && \"Unexpected base class!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3044, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected base class!");
3045	const CXXRecordDecl *Base =
3046	cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3047
3048	// If the base is after the span we care about, ignore it.
3049	unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3050	if (BaseOffset >= EndBit) continue;
3051
3052	unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3053	if (!BitsContainNoUserData(I.getType(), BaseStart,
3054	EndBit-BaseOffset, Context))
3055	return false;
3056	}
3057	}
3058
3059	// Verify that no field has data that overlaps the region of interest. Yes
3060	// this could be sped up a lot by being smarter about queried fields,
3061	// however we're only looking at structs up to 16 bytes, so we don't care
3062	// much.
3063	unsigned idx = 0;
3064	for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3065	i != e; ++i, ++idx) {
3066	unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3067
3068	// If we found a field after the region we care about, then we're done.
3069	if (FieldOffset >= EndBit) break;
3070
3071	unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3072	if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3073	Context))
3074	return false;
3075	}
3076
3077	// If nothing in this record overlapped the area of interest, then we're
3078	// clean.
3079	return true;
3080	}
3081
3082	return false;
3083	}
3084
3085	/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3086	/// float member at the specified offset. For example, {int,{float}} has a
3087	/// float at offset 4. It is conservatively correct for this routine to return
3088	/// false.
3089	static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3090	const llvm::DataLayout &TD) {
3091	// Base case if we find a float.
3092	if (IROffset == 0 && IRType->isFloatTy())
3093	return true;
3094
3095	// If this is a struct, recurse into the field at the specified offset.
3096	if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3097	const llvm::StructLayout *SL = TD.getStructLayout(STy);
3098	unsigned Elt = SL->getElementContainingOffset(IROffset);
3099	IROffset -= SL->getElementOffset(Elt);
3100	return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3101	}
3102
3103	// If this is an array, recurse into the field at the specified offset.
3104	if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3105	llvm::Type *EltTy = ATy->getElementType();
3106	unsigned EltSize = TD.getTypeAllocSize(EltTy);
3107	IROffset -= IROffset/EltSize*EltSize;
3108	return ContainsFloatAtOffset(EltTy, IROffset, TD);
3109	}
3110
3111	return false;
3112	}
3113
3114
3115	/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3116	/// low 8 bytes of an XMM register, corresponding to the SSE class.
3117	llvm::Type *X86_64ABIInfo::
3118	GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3119	QualType SourceTy, unsigned SourceOffset) const {
3120	// The only three choices we have are either double, <2 x float>, or float. We
3121	// pass as float if the last 4 bytes is just padding. This happens for
3122	// structs that contain 3 floats.
3123	if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3124	SourceOffset*8+64, getContext()))
3125	return llvm::Type::getFloatTy(getVMContext());
3126
3127	// We want to pass as <2 x float> if the LLVM IR type contains a float at
3128	// offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3129	// case.
3130	if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3131	ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3132	return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3133
3134	return llvm::Type::getDoubleTy(getVMContext());
3135	}
3136
3137
3138	/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3139	/// an 8-byte GPR. This means that we either have a scalar or we are talking
3140	/// about the high or low part of an up-to-16-byte struct. This routine picks
3141	/// the best LLVM IR type to represent this, which may be i64 or may be anything
3142	/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3143	/// etc).
3144	///
3145	/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3146	/// the source type. IROffset is an offset in bytes into the LLVM IR type that
3147	/// the 8-byte value references. PrefType may be null.
3148	///
3149	/// SourceTy is the source-level type for the entire argument. SourceOffset is
3150	/// an offset into this that we're processing (which is always either 0 or 8).
3151	///
3152	llvm::Type *X86_64ABIInfo::
3153	GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3154	QualType SourceTy, unsigned SourceOffset) const {
3155	// If we're dealing with an un-offset LLVM IR type, then it means that we're
3156	// returning an 8-byte unit starting with it. See if we can safely use it.
3157	if (IROffset == 0) {
3158	// Pointers and int64's always fill the 8-byte unit.
3159	if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) \|\|
3160	IRType->isIntegerTy(64))
3161	return IRType;
3162
3163	// If we have a 1/2/4-byte integer, we can use it only if the rest of the
3164	// goodness in the source type is just tail padding. This is allowed to
3165	// kick in for struct {double,int} on the int, but not on
3166	// struct{double,int,int} because we wouldn't return the second int. We
3167	// have to do this analysis on the source type because we can't depend on
3168	// unions being lowered a specific way etc.
3169	if (IRType->isIntegerTy(8) \|\| IRType->isIntegerTy(16) \|\|
3170	IRType->isIntegerTy(32) \|\|
3171	(isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3172	unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3173	cast<llvm::IntegerType>(IRType)->getBitWidth();
3174
3175	if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3176	SourceOffset*8+64, getContext()))
3177	return IRType;
3178	}
3179	}
3180
3181	if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3182	// If this is a struct, recurse into the field at the specified offset.
3183	const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3184	if (IROffset < SL->getSizeInBytes()) {
3185	unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3186	IROffset -= SL->getElementOffset(FieldIdx);
3187
3188	return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3189	SourceTy, SourceOffset);
3190	}
3191	}
3192
3193	if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3194	llvm::Type *EltTy = ATy->getElementType();
3195	unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3196	unsigned EltOffset = IROffset/EltSize*EltSize;
3197	return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3198	SourceOffset);
3199	}
3200
3201	// Okay, we don't have any better idea of what to pass, so we pass this in an
3202	// integer register that isn't too big to fit the rest of the struct.
3203	unsigned TySizeInBytes =
3204	(unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3205
3206	(0) . __assert_fail ("TySizeInBytes != SourceOffset && \"Empty field?\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3206, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(TySizeInBytes != SourceOffset && "Empty field?");
3207
3208	// It is always safe to classify this as an integer type up to i64 that
3209	// isn't larger than the structure.
3210	return llvm::IntegerType::get(getVMContext(),
3211	std::min(TySizeInBytes-SourceOffset, 8U)*8);
3212	}
3213
3214
3215	/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3216	/// be used as elements of a two register pair to pass or return, return a
3217	/// first class aggregate to represent them. For example, if the low part of
3218	/// a by-value argument should be passed as i32* and the high part as float,
3219	/// return {i32*, float}.
3220	static llvm::Type *
3221	GetX86_64ByValArgumentPair(llvm::Type Lo, llvm::Type Hi,
3222	const llvm::DataLayout &TD) {
3223	// In order to correctly satisfy the ABI, we need to the high part to start
3224	// at offset 8. If the high and low parts we inferred are both 4-byte types
3225	// (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3226	// the second element at offset 8. Check for this:
3227	unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3228	unsigned HiAlign = TD.getABITypeAlignment(Hi);
3229	unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3230	(0) . __assert_fail ("HiStart != 0 && HiStart <= 8 && \"Invalid x86-64 argument pair!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3230, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3231
3232	// To handle this, we have to increase the size of the low part so that the
3233	// second element will start at an 8 byte offset. We can't increase the size
3234	// of the second element because it might make us access off the end of the
3235	// struct.
3236	if (HiStart != 8) {
3237	// There are usually two sorts of types the ABI generation code can produce
3238	// for the low part of a pair that aren't 8 bytes in size: float or
3239	// i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3240	// NaCl).
3241	// Promote these to a larger type.
3242	if (Lo->isFloatTy())
3243	Lo = llvm::Type::getDoubleTy(Lo->getContext());
3244	else {
3245	(0) . __assert_fail ("(Lo->isIntegerTy() \|\| Lo->isPointerTy()) && \"Invalid/unknown lo type\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3246, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Lo->isIntegerTy() \|\| Lo->isPointerTy())
3246	(0) . __assert_fail ("(Lo->isIntegerTy() \|\| Lo->isPointerTy()) && \"Invalid/unknown lo type\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3246, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> && "Invalid/unknown lo type");
3247	Lo = llvm::Type::getInt64Ty(Lo->getContext());
3248	}
3249	}
3250
3251	llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3252
3253	// Verify that the second element is at an 8-byte offset.
3254	(0) . __assert_fail ("TD.getStructLayout(Result)->getElementOffset(1) == 8 && \"Invalid x86-64 argument pair!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3255, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3255	(0) . __assert_fail ("TD.getStructLayout(Result)->getElementOffset(1) == 8 && \"Invalid x86-64 argument pair!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3255, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Invalid x86-64 argument pair!");
3256	return Result;
3257	}
3258
3259	ABIArgInfo X86_64ABIInfo::
3260	classifyReturnType(QualType RetTy) const {
3261	// AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3262	// classification algorithm.
3263	X86_64ABIInfo::Class Lo, Hi;
3264	classify(RetTy, 0, Lo, Hi, /isNamedArg/ true);
3265
3266	// Check some invariants.
3267	(0) . __assert_fail ("(Hi != Memory \|\| Lo == Memory) && \"Invalid memory classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3267, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi != Memory \|\| Lo == Memory) && "Invalid memory classification.");
3268	(0) . __assert_fail ("(Hi != SSEUp \|\| Lo == SSE) && \"Invalid SSEUp classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3268, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi != SSEUp \|\| Lo == SSE) && "Invalid SSEUp classification.");
3269
3270	llvm::Type *ResType = nullptr;
3271	switch (Lo) {
3272	case NoClass:
3273	if (Hi == NoClass)
3274	return ABIArgInfo::getIgnore();
3275	// If the low part is just padding, it takes no register, leave ResType
3276	// null.
3277	(0) . __assert_fail ("(Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) && \"Unknown missing lo part\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3278, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) &&
3278	(0) . __assert_fail ("(Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) && \"Unknown missing lo part\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3278, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unknown missing lo part");
3279	break;
3280
3281	case SSEUp:
3282	case X87Up:
3283	llvm_unreachable("Invalid classification for lo word.");
3284
3285	// AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3286	// hidden argument.
3287	case Memory:
3288	return getIndirectReturnResult(RetTy);
3289
3290	// AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3291	// available register of the sequence %rax, %rdx is used.
3292	case Integer:
3293	ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3294
3295	// If we have a sign or zero extended integer, make sure to return Extend
3296	// so that the parameter gets the right LLVM IR attributes.
3297	if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3298	// Treat an enum type as its underlying type.
3299	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3300	RetTy = EnumTy->getDecl()->getIntegerType();
3301
3302	if (RetTy->isIntegralOrEnumerationType() &&
3303	RetTy->isPromotableIntegerType())
3304	return ABIArgInfo::getExtend(RetTy);
3305	}
3306	break;
3307
3308	// AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3309	// available SSE register of the sequence %xmm0, %xmm1 is used.
3310	case SSE:
3311	ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3312	break;
3313
3314	// AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3315	// returned on the X87 stack in %st0 as 80-bit x87 number.
3316	case X87:
3317	ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3318	break;
3319
3320	// AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3321	// part of the value is returned in %st0 and the imaginary part in
3322	// %st1.
3323	case ComplexX87:
3324	(0) . __assert_fail ("Hi == ComplexX87 && \"Unexpected ComplexX87 classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3324, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3325	ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3326	llvm::Type::getX86_FP80Ty(getVMContext()));
3327	break;
3328	}
3329
3330	llvm::Type *HighPart = nullptr;
3331	switch (Hi) {
3332	// Memory was handled previously and X87 should
3333	// never occur as a hi class.
3334	case Memory:
3335	case X87:
3336	llvm_unreachable("Invalid classification for hi word.");
3337
3338	case ComplexX87: // Previously handled.
3339	case NoClass:
3340	break;
3341
3342	case Integer:
3343	HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3344	if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3345	return ABIArgInfo::getDirect(HighPart, 8);
3346	break;
3347	case SSE:
3348	HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3349	if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3350	return ABIArgInfo::getDirect(HighPart, 8);
3351	break;
3352
3353	// AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3354	// is passed in the next available eightbyte chunk if the last used
3355	// vector register.
3356	//
3357	// SSEUP should always be preceded by SSE, just widen.
3358	case SSEUp:
3359	(0) . __assert_fail ("Lo == SSE && \"Unexpected SSEUp classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3359, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Lo == SSE && "Unexpected SSEUp classification.");
3360	ResType = GetByteVectorType(RetTy);
3361	break;
3362
3363	// AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3364	// returned together with the previous X87 value in %st0.
3365	case X87Up:
3366	// If X87Up is preceded by X87, we don't need to do
3367	// anything. However, in some cases with unions it may not be
3368	// preceded by X87. In such situations we follow gcc and pass the
3369	// extra bits in an SSE reg.
3370	if (Lo != X87) {
3371	HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3372	if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3373	return ABIArgInfo::getDirect(HighPart, 8);
3374	}
3375	break;
3376	}
3377
3378	// If a high part was specified, merge it together with the low part. It is
3379	// known to pass in the high eightbyte of the result. We do this by forming a
3380	// first class struct aggregate with the high and low part: {low, high}
3381	if (HighPart)
3382	ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3383
3384	return ABIArgInfo::getDirect(ResType);
3385	}
3386
3387	ABIArgInfo X86_64ABIInfo::classifyArgumentType(
3388	QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3389	bool isNamedArg)
3390	const
3391	{
3392	Ty = useFirstFieldIfTransparentUnion(Ty);
3393
3394	X86_64ABIInfo::Class Lo, Hi;
3395	classify(Ty, 0, Lo, Hi, isNamedArg);
3396
3397	// Check some invariants.
3398	// FIXME: Enforce these by construction.
3399	(0) . __assert_fail ("(Hi != Memory \|\| Lo == Memory) && \"Invalid memory classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3399, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi != Memory \|\| Lo == Memory) && "Invalid memory classification.");
3400	(0) . __assert_fail ("(Hi != SSEUp \|\| Lo == SSE) && \"Invalid SSEUp classification.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3400, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi != SSEUp \|\| Lo == SSE) && "Invalid SSEUp classification.");
3401
3402	neededInt = 0;
3403	neededSSE = 0;
3404	llvm::Type *ResType = nullptr;
3405	switch (Lo) {
3406	case NoClass:
3407	if (Hi == NoClass)
3408	return ABIArgInfo::getIgnore();
3409	// If the low part is just padding, it takes no register, leave ResType
3410	// null.
3411	(0) . __assert_fail ("(Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) && \"Unknown missing lo part\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3412, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) &&
3412	(0) . __assert_fail ("(Hi == SSE \|\| Hi == Integer \|\| Hi == X87Up) && \"Unknown missing lo part\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3412, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unknown missing lo part");
3413	break;
3414
3415	// AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3416	// on the stack.
3417	case Memory:
3418
3419	// AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3420	// COMPLEX_X87, it is passed in memory.
3421	case X87:
3422	case ComplexX87:
3423	if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3424	++neededInt;
3425	return getIndirectResult(Ty, freeIntRegs);
3426
3427	case SSEUp:
3428	case X87Up:
3429	llvm_unreachable("Invalid classification for lo word.");
3430
3431	// AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3432	// available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3433	// and %r9 is used.
3434	case Integer:
3435	++neededInt;
3436
3437	// Pick an 8-byte type based on the preferred type.
3438	ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3439
3440	// If we have a sign or zero extended integer, make sure to return Extend
3441	// so that the parameter gets the right LLVM IR attributes.
3442	if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3443	// Treat an enum type as its underlying type.
3444	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3445	Ty = EnumTy->getDecl()->getIntegerType();
3446
3447	if (Ty->isIntegralOrEnumerationType() &&
3448	Ty->isPromotableIntegerType())
3449	return ABIArgInfo::getExtend(Ty);
3450	}
3451
3452	break;
3453
3454	// AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3455	// available SSE register is used, the registers are taken in the
3456	// order from %xmm0 to %xmm7.
3457	case SSE: {
3458	llvm::Type *IRType = CGT.ConvertType(Ty);
3459	ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3460	++neededSSE;
3461	break;
3462	}
3463	}
3464
3465	llvm::Type *HighPart = nullptr;
3466	switch (Hi) {
3467	// Memory was handled previously, ComplexX87 and X87 should
3468	// never occur as hi classes, and X87Up must be preceded by X87,
3469	// which is passed in memory.
3470	case Memory:
3471	case X87:
3472	case ComplexX87:
3473	llvm_unreachable("Invalid classification for hi word.");
3474
3475	case NoClass: break;
3476
3477	case Integer:
3478	++neededInt;
3479	// Pick an 8-byte type based on the preferred type.
3480	HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3481
3482	if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3483	return ABIArgInfo::getDirect(HighPart, 8);
3484	break;
3485
3486	// X87Up generally doesn't occur here (long double is passed in
3487	// memory), except in situations involving unions.
3488	case X87Up:
3489	case SSE:
3490	HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3491
3492	if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3493	return ABIArgInfo::getDirect(HighPart, 8);
3494
3495	++neededSSE;
3496	break;
3497
3498	// AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3499	// eightbyte is passed in the upper half of the last used SSE
3500	// register. This only happens when 128-bit vectors are passed.
3501	case SSEUp:
3502	(0) . __assert_fail ("Lo == SSE && \"Unexpected SSEUp classification\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3502, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Lo == SSE && "Unexpected SSEUp classification");
3503	ResType = GetByteVectorType(Ty);
3504	break;
3505	}
3506
3507	// If a high part was specified, merge it together with the low part. It is
3508	// known to pass in the high eightbyte of the result. We do this by forming a
3509	// first class struct aggregate with the high and low part: {low, high}
3510	if (HighPart)
3511	ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3512
3513	return ABIArgInfo::getDirect(ResType);
3514	}
3515
3516	ABIArgInfo
3517	X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3518	unsigned &NeededSSE) const {
3519	auto RT = Ty->getAs<RecordType>();
3520	(0) . __assert_fail ("RT && \"classifyRegCallStructType only valid with struct types\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3520, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(RT && "classifyRegCallStructType only valid with struct types");
3521
3522	if (RT->getDecl()->hasFlexibleArrayMember())
3523	return getIndirectReturnResult(Ty);
3524
3525	// Sum up bases
3526	if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3527	if (CXXRD->isDynamicClass()) {
3528	NeededInt = NeededSSE = 0;
3529	return getIndirectReturnResult(Ty);
3530	}
3531
3532	for (const auto &I : CXXRD->bases())
3533	if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3534	.isIndirect()) {
3535	NeededInt = NeededSSE = 0;
3536	return getIndirectReturnResult(Ty);
3537	}
3538	}
3539
3540	// Sum up members
3541	for (const auto *FD : RT->getDecl()->fields()) {
3542	if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3543	if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3544	.isIndirect()) {
3545	NeededInt = NeededSSE = 0;
3546	return getIndirectReturnResult(Ty);
3547	}
3548	} else {
3549	unsigned LocalNeededInt, LocalNeededSSE;
3550	if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3551	LocalNeededSSE, true)
3552	.isIndirect()) {
3553	NeededInt = NeededSSE = 0;
3554	return getIndirectReturnResult(Ty);
3555	}
3556	NeededInt += LocalNeededInt;
3557	NeededSSE += LocalNeededSSE;
3558	}
3559	}
3560
3561	return ABIArgInfo::getDirect();
3562	}
3563
3564	ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3565	unsigned &NeededInt,
3566	unsigned &NeededSSE) const {
3567
3568	NeededInt = 0;
3569	NeededSSE = 0;
3570
3571	return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3572	}
3573
3574	void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3575
3576	const unsigned CallingConv = FI.getCallingConvention();
3577	// It is possible to force Win64 calling convention on any x86_64 target by
3578	// using __attribute__((ms_abi)). In such case to correctly emit Win64
3579	// compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3580	if (CallingConv == llvm::CallingConv::Win64) {
3581	WinX86_64ABIInfo Win64ABIInfo(CGT);
3582	Win64ABIInfo.computeInfo(FI);
3583	return;
3584	}
3585
3586	bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3587
3588	// Keep track of the number of assigned registers.
3589	unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3590	unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3591	unsigned NeededInt, NeededSSE;
3592
3593	if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3594	if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3595	!FI.getReturnType()->getTypePtr()->isUnionType()) {
3596	FI.getReturnInfo() =
3597	classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3598	if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3599	FreeIntRegs -= NeededInt;
3600	FreeSSERegs -= NeededSSE;
3601	} else {
3602	FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3603	}
3604	} else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3605	// Complex Long Double Type is passed in Memory when Regcall
3606	// calling convention is used.
3607	const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3608	if (getContext().getCanonicalType(CT->getElementType()) ==
3609	getContext().LongDoubleTy)
3610	FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3611	} else
3612	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3613	}
3614
3615	// If the return value is indirect, then the hidden argument is consuming one
3616	// integer register.
3617	if (FI.getReturnInfo().isIndirect())
3618	--FreeIntRegs;
3619
3620	// The chain argument effectively gives us another free register.
3621	if (FI.isChainCall())
3622	++FreeIntRegs;
3623
3624	unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3625	// AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3626	// get assigned (in left-to-right order) for passing as follows...
3627	unsigned ArgNo = 0;
3628	for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3629	it != ie; ++it, ++ArgNo) {
3630	bool IsNamedArg = ArgNo < NumRequiredArgs;
3631
3632	if (IsRegCall && it->type->isStructureOrClassType())
3633	it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3634	else
3635	it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3636	NeededSSE, IsNamedArg);
3637
3638	// AMD64-ABI 3.2.3p3: If there are no registers available for any
3639	// eightbyte of an argument, the whole argument is passed on the
3640	// stack. If registers have already been assigned for some
3641	// eightbytes of such an argument, the assignments get reverted.
3642	if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3643	FreeIntRegs -= NeededInt;
3644	FreeSSERegs -= NeededSSE;
3645	} else {
3646	it->info = getIndirectResult(it->type, FreeIntRegs);
3647	}
3648	}
3649	}
3650
3651	static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
3652	Address VAListAddr, QualType Ty) {
3653	Address overflow_arg_area_p =
3654	CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
3655	llvm::Value *overflow_arg_area =
3656	CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3657
3658	// AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3659	// byte boundary if alignment needed by type exceeds 8 byte boundary.
3660	// It isn't stated explicitly in the standard, but in practice we use
3661	// alignment greater than 16 where necessary.
3662	CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3663	if (Align > CharUnits::fromQuantity(8)) {
3664	overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3665	Align);
3666	}
3667
3668	// AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3669	llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3670	llvm::Value *Res =
3671	CGF.Builder.CreateBitCast(overflow_arg_area,
3672	llvm::PointerType::getUnqual(LTy));
3673
3674	// AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3675	// l->overflow_arg_area + sizeof(type).
3676	// AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3677	// an 8 byte boundary.
3678
3679	uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3680	llvm::Value *Offset =
3681	llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3682	overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3683	"overflow_arg_area.next");
3684	CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3685
3686	// AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3687	return Address(Res, Align);
3688	}
3689
3690	Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3691	QualType Ty) const {
3692	// Assume that va_list type is correct; should be pointer to LLVM type:
3693	// struct {
3694	// i32 gp_offset;
3695	// i32 fp_offset;
3696	// i8* overflow_arg_area;
3697	// i8* reg_save_area;
3698	// };
3699	unsigned neededInt, neededSSE;
3700
3701	Ty = getContext().getCanonicalType(Ty);
3702	ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3703	/isNamedArg/false);
3704
3705	// AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3706	// in the registers. If not go to step 7.
3707	if (!neededInt && !neededSSE)
3708	return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3709
3710	// AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3711	// general purpose registers needed to pass type and num_fp to hold
3712	// the number of floating point registers needed.
3713
3714	// AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3715	// registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3716	// l->fp_offset > 304 - num_fp * 16 go to step 7.
3717	//
3718	// NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3719	// register save space).
3720
3721	llvm::Value *InRegs = nullptr;
3722	Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3723	llvm::Value gp_offset = nullptr, fp_offset = nullptr;
3724	if (neededInt) {
3725	gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
3726	gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3727	InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3728	InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3729	}
3730
3731	if (neededSSE) {
3732	fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
3733	fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3734	llvm::Value *FitsInFP =
3735	llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3736	FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3737	InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3738	}
3739
3740	llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3741	llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3742	llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3743	CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3744
3745	// Emit code to load the value if it was passed in registers.
3746
3747	CGF.EmitBlock(InRegBlock);
3748
3749	// AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3750	// an offset of l->gp_offset and/or l->fp_offset. This may require
3751	// copying to a temporary location in case the parameter is passed
3752	// in different register classes or requires an alignment greater
3753	// than 8 for general purpose registers and 16 for XMM registers.
3754	//
3755	// FIXME: This really results in shameful code when we end up needing to
3756	// collect arguments from different places; often what should result in a
3757	// simple assembling of a structure from scattered addresses has many more
3758	// loads than necessary. Can we clean this up?
3759	llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3760	llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3761	CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
3762
3763	Address RegAddr = Address::invalid();
3764	if (neededInt && neededSSE) {
3765	// FIXME: Cleanup.
3766	(0) . __assert_fail ("AI.isDirect() && \"Unexpected ABI info for mixed regs\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3766, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3767	llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3768	Address Tmp = CGF.CreateMemTemp(Ty);
3769	Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3770	(0) . __assert_fail ("ST->getNumElements() == 2 && \"Unexpected ABI info for mixed regs\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3770, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3771	llvm::Type *TyLo = ST->getElementType(0);
3772	llvm::Type *TyHi = ST->getElementType(1);
3773	(0) . __assert_fail ("(TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && \"Unexpected ABI info for mixed regs\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3774, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3774	(0) . __assert_fail ("(TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && \"Unexpected ABI info for mixed regs\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3774, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Unexpected ABI info for mixed regs");
3775	llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3776	llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3777	llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3778	llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3779	llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3780	llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3781
3782	// Copy the first element.
3783	// FIXME: Our choice of alignment here and below is probably pessimistic.
3784	llvm::Value *V = CGF.Builder.CreateAlignedLoad(
3785	TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3786	CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3787	CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3788
3789	// Copy the second element.
3790	V = CGF.Builder.CreateAlignedLoad(
3791	TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3792	CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3793	CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3794
3795	RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3796	} else if (neededInt) {
3797	RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3798	CharUnits::fromQuantity(8));
3799	RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3800
3801	// Copy to a temporary if necessary to ensure the appropriate alignment.
3802	std::pair<CharUnits, CharUnits> SizeAlign =
3803	getContext().getTypeInfoInChars(Ty);
3804	uint64_t TySize = SizeAlign.first.getQuantity();
3805	CharUnits TyAlign = SizeAlign.second;
3806
3807	// Copy into a temporary if the type is more aligned than the
3808	// register save area.
3809	if (TyAlign.getQuantity() > 8) {
3810	Address Tmp = CGF.CreateMemTemp(Ty);
3811	CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3812	RegAddr = Tmp;
3813	}
3814
3815	} else if (neededSSE == 1) {
3816	RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3817	CharUnits::fromQuantity(16));
3818	RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3819	} else {
3820	(0) . __assert_fail ("neededSSE == 2 && \"Invalid number of needed registers!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 3820, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(neededSSE == 2 && "Invalid number of needed registers!");
3821	// SSE registers are spaced 16 bytes apart in the register save
3822	// area, we need to collect the two eightbytes together.
3823	// The ABI isn't explicit about this, but it seems reasonable
3824	// to assume that the slots are 16-byte aligned, since the stack is
3825	// naturally 16-byte aligned and the prologue is expected to store
3826	// all the SSE registers to the RSA.
3827	Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3828	CharUnits::fromQuantity(16));
3829	Address RegAddrHi =
3830	CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3831	CharUnits::fromQuantity(16));
3832	llvm::Type *ST = AI.canHaveCoerceToType()
3833	? AI.getCoerceToType()
3834	: llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3835	llvm::Value *V;
3836	Address Tmp = CGF.CreateMemTemp(Ty);
3837	Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3838	V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3839	RegAddrLo, ST->getStructElementType(0)));
3840	CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
3841	V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
3842	RegAddrHi, ST->getStructElementType(1)));
3843	CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
3844
3845	RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3846	}
3847
3848	// AMD64-ABI 3.5.7p5: Step 5. Set:
3849	// l->gp_offset = l->gp_offset + num_gp * 8
3850	// l->fp_offset = l->fp_offset + num_fp * 16.
3851	if (neededInt) {
3852	llvm::Value Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt 8);
3853	CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3854	gp_offset_p);
3855	}
3856	if (neededSSE) {
3857	llvm::Value Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE 16);
3858	CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3859	fp_offset_p);
3860	}
3861	CGF.EmitBranch(ContBlock);
3862
3863	// Emit code to load the value if it was passed in memory.
3864
3865	CGF.EmitBlock(InMemBlock);
3866	Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3867
3868	// Return the appropriate result.
3869
3870	CGF.EmitBlock(ContBlock);
3871	Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3872	"vaarg.addr");
3873	return ResAddr;
3874	}
3875
3876	Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3877	QualType Ty) const {
3878	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /indirect/ false,
3879	CGF.getContext().getTypeInfoInChars(Ty),
3880	CharUnits::fromQuantity(8),
3881	/allowHigherAlign/ false);
3882	}
3883
3884	ABIArgInfo
3885	WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3886	const ABIArgInfo &current) const {
3887	// Assumes vectorCall calling convention.
3888	const Type *Base = nullptr;
3889	uint64_t NumElts = 0;
3890
3891	if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3892	isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3893	FreeSSERegs -= NumElts;
3894	return getDirectX86Hva();
3895	}
3896	return current;
3897	}
3898
3899	ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3900	bool IsReturnType, bool IsVectorCall,
3901	bool IsRegCall) const {
3902
3903	if (Ty->isVoidType())
3904	return ABIArgInfo::getIgnore();
3905
3906	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3907	Ty = EnumTy->getDecl()->getIntegerType();
3908
3909	TypeInfo Info = getContext().getTypeInfo(Ty);
3910	uint64_t Width = Info.Width;
3911	CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3912
3913	const RecordType *RT = Ty->getAs<RecordType>();
3914	if (RT) {
3915	if (!IsReturnType) {
3916	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3917	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3918	}
3919
3920	if (RT->getDecl()->hasFlexibleArrayMember())
3921	return getNaturalAlignIndirect(Ty, /ByVal=/false);
3922
3923	}
3924
3925	const Type *Base = nullptr;
3926	uint64_t NumElts = 0;
3927	// vectorcall adds the concept of a homogenous vector aggregate, similar to
3928	// other targets.
3929	if ((IsVectorCall \|\| IsRegCall) &&
3930	isHomogeneousAggregate(Ty, Base, NumElts)) {
3931	if (IsRegCall) {
3932	if (FreeSSERegs >= NumElts) {
3933	FreeSSERegs -= NumElts;
3934	if (IsReturnType \|\| Ty->isBuiltinType() \|\| Ty->isVectorType())
3935	return ABIArgInfo::getDirect();
3936	return ABIArgInfo::getExpand();
3937	}
3938	return ABIArgInfo::getIndirect(Align, /ByVal=/false);
3939	} else if (IsVectorCall) {
3940	if (FreeSSERegs >= NumElts &&
3941	(IsReturnType \|\| Ty->isBuiltinType() \|\| Ty->isVectorType())) {
3942	FreeSSERegs -= NumElts;
3943	return ABIArgInfo::getDirect();
3944	} else if (IsReturnType) {
3945	return ABIArgInfo::getExpand();
3946	} else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3947	// HVAs are delayed and reclassified in the 2nd step.
3948	return ABIArgInfo::getIndirect(Align, /ByVal=/false);
3949	}
3950	}
3951	}
3952
3953	if (Ty->isMemberPointerType()) {
3954	// If the member pointer is represented by an LLVM int or ptr, pass it
3955	// directly.
3956	llvm::Type *LLTy = CGT.ConvertType(Ty);
3957	if (LLTy->isPointerTy() \|\| LLTy->isIntegerTy())
3958	return ABIArgInfo::getDirect();
3959	}
3960
3961	if (RT \|\| Ty->isAnyComplexType() \|\| Ty->isMemberPointerType()) {
3962	// MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3963	// not 1, 2, 4, or 8 bytes, must be passed by reference."
3964	if (Width > 64 \|\| !llvm::isPowerOf2_64(Width))
3965	return getNaturalAlignIndirect(Ty, /ByVal=/false);
3966
3967	// Otherwise, coerce it to a small integer.
3968	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3969	}
3970
3971	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3972	switch (BT->getKind()) {
3973	case BuiltinType::Bool:
3974	// Bool type is always extended to the ABI, other builtin types are not
3975	// extended.
3976	return ABIArgInfo::getExtend(Ty);
3977
3978	case BuiltinType::LongDouble:
3979	// Mingw64 GCC uses the old 80 bit extended precision floating point
3980	// unit. It passes them indirectly through memory.
3981	if (IsMingw64) {
3982	const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3983	if (LDF == &llvm::APFloat::x87DoubleExtended())
3984	return ABIArgInfo::getIndirect(Align, /ByVal=/false);
3985	}
3986	break;
3987
3988	case BuiltinType::Int128:
3989	case BuiltinType::UInt128:
3990	// If it's a parameter type, the normal ABI rule is that arguments larger
3991	// than 8 bytes are passed indirectly. GCC follows it. We follow it too,
3992	// even though it isn't particularly efficient.
3993	if (!IsReturnType)
3994	return ABIArgInfo::getIndirect(Align, /ByVal=/false);
3995
3996	// Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
3997	// Clang matches them for compatibility.
3998	return ABIArgInfo::getDirect(
3999	llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2));
4000
4001	default:
4002	break;
4003	}
4004	}
4005
4006	return ABIArgInfo::getDirect();
4007	}
4008
4009	void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
4010	unsigned FreeSSERegs,
4011	bool IsVectorCall,
4012	bool IsRegCall) const {
4013	unsigned Count = 0;
4014	for (auto &I : FI.arguments()) {
4015	// Vectorcall in x64 only permits the first 6 arguments to be passed
4016	// as XMM/YMM registers.
4017	if (Count < VectorcallMaxParamNumAsReg)
4018	I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4019	else {
4020	// Since these cannot be passed in registers, pretend no registers
4021	// are left.
4022	unsigned ZeroSSERegsAvail = 0;
4023	I.info = classify(I.type, /FreeSSERegs=/ZeroSSERegsAvail, false,
4024	IsVectorCall, IsRegCall);
4025	}
4026	++Count;
4027	}
4028
4029	for (auto &I : FI.arguments()) {
4030	I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
4031	}
4032	}
4033
4034	void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4035	bool IsVectorCall =
4036	FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
4037	bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
4038
4039	unsigned FreeSSERegs = 0;
4040	if (IsVectorCall) {
4041	// We can use up to 4 SSE return registers with vectorcall.
4042	FreeSSERegs = 4;
4043	} else if (IsRegCall) {
4044	// RegCall gives us 16 SSE registers.
4045	FreeSSERegs = 16;
4046	}
4047
4048	if (!getCXXABI().classifyReturnType(FI))
4049	FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4050	IsVectorCall, IsRegCall);
4051
4052	if (IsVectorCall) {
4053	// We can use up to 6 SSE register parameters with vectorcall.
4054	FreeSSERegs = 6;
4055	} else if (IsRegCall) {
4056	// RegCall gives us 16 SSE registers, we can reuse the return registers.
4057	FreeSSERegs = 16;
4058	}
4059
4060	if (IsVectorCall) {
4061	computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4062	} else {
4063	for (auto &I : FI.arguments())
4064	I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4065	}
4066
4067	}
4068
4069	Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4070	QualType Ty) const {
4071
4072	bool IsIndirect = false;
4073
4074	// MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4075	// not 1, 2, 4, or 8 bytes, must be passed by reference."
4076	if (isAggregateTypeForABI(Ty) \|\| Ty->isMemberPointerType()) {
4077	uint64_t Width = getContext().getTypeSize(Ty);
4078	IsIndirect = Width > 64 \|\| !llvm::isPowerOf2_64(Width);
4079	}
4080
4081	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4082	CGF.getContext().getTypeInfoInChars(Ty),
4083	CharUnits::fromQuantity(8),
4084	/allowHigherAlign/ false);
4085	}
4086
4087	// PowerPC-32
4088	namespace {
4089	/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4090	class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4091	bool IsSoftFloatABI;
4092
4093	CharUnits getParamTypeAlignment(QualType Ty) const;
4094
4095	public:
4096	PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4097	: DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4098
4099	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4100	QualType Ty) const override;
4101	};
4102
4103	class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4104	public:
4105	PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4106	: TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4107
4108	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4109	// This is recovered from gcc output.
4110	return 1; // r1 is the dedicated stack pointer
4111	}
4112
4113	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4114	llvm::Value *Address) const override;
4115	};
4116	}
4117
4118	CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4119	// Complex types are passed just like their elements
4120	if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4121	Ty = CTy->getElementType();
4122
4123	if (Ty->isVectorType())
4124	return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4125	: 4);
4126
4127	// For single-element float/vector structs, we consider the whole type
4128	// to have the same alignment requirements as its single element.
4129	const Type *AlignTy = nullptr;
4130	if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4131	const BuiltinType *BT = EltType->getAs<BuiltinType>();
4132	if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) \|\|
4133	(BT && BT->isFloatingPoint()))
4134	AlignTy = EltType;
4135	}
4136
4137	if (AlignTy)
4138	return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4139	return CharUnits::fromQuantity(4);
4140	}
4141
4142	// TODO: this implementation is now likely redundant with
4143	// DefaultABIInfo::EmitVAArg.
4144	Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4145	QualType Ty) const {
4146	if (getTarget().getTriple().isOSDarwin()) {
4147	auto TI = getContext().getTypeInfoInChars(Ty);
4148	TI.second = getParamTypeAlignment(Ty);
4149
4150	CharUnits SlotSize = CharUnits::fromQuantity(4);
4151	return emitVoidPtrVAArg(CGF, VAList, Ty,
4152	classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4153	/AllowHigherAlign=/true);
4154	}
4155
4156	const unsigned OverflowLimit = 8;
4157	if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4158	// TODO: Implement this. For now ignore.
4159	(void)CTy;
4160	return Address::invalid(); // FIXME?
4161	}
4162
4163	// struct __va_list_tag {
4164	// unsigned char gpr;
4165	// unsigned char fpr;
4166	// unsigned short reserved;
4167	// void *overflow_arg_area;
4168	// void *reg_save_area;
4169	// };
4170
4171	bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4172	bool isInt =
4173	Ty->isIntegerType() \|\| Ty->isPointerType() \|\| Ty->isAggregateType();
4174	bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4175
4176	// All aggregates are passed indirectly? That doesn't seem consistent
4177	// with the argument-lowering code.
4178	bool isIndirect = Ty->isAggregateType();
4179
4180	CGBuilderTy &Builder = CGF.Builder;
4181
4182	// The calling convention either uses 1-2 GPRs or 1 FPR.
4183	Address NumRegsAddr = Address::invalid();
4184	if (isInt \|\| IsSoftFloatABI) {
4185	NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4186	} else {
4187	NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4188	}
4189
4190	llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4191
4192	// "Align" the register count when TY is i64.
4193	if (isI64 \|\| (isF64 && IsSoftFloatABI)) {
4194	NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4195	NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4196	}
4197
4198	llvm::Value *CC =
4199	Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4200
4201	llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4202	llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4203	llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4204
4205	Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4206
4207	llvm::Type *DirectTy = CGF.ConvertType(Ty);
4208	if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4209
4210	// Case 1: consume registers.
4211	Address RegAddr = Address::invalid();
4212	{
4213	CGF.EmitBlock(UsingRegs);
4214
4215	Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4216	RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4217	CharUnits::fromQuantity(8));
4218	assert(RegAddr.getElementType() == CGF.Int8Ty);
4219
4220	// Floating-point registers start after the general-purpose registers.
4221	if (!(isInt \|\| IsSoftFloatABI)) {
4222	RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4223	CharUnits::fromQuantity(32));
4224	}
4225
4226	// Get the address of the saved value by scaling the number of
4227	// registers we've used by the number of
4228	CharUnits RegSize = CharUnits::fromQuantity((isInt \|\| IsSoftFloatABI) ? 4 : 8);
4229	llvm::Value *RegOffset =
4230	Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4231	RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4232	RegAddr.getPointer(), RegOffset),
4233	RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4234	RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4235
4236	// Increase the used-register count.
4237	NumRegs =
4238	Builder.CreateAdd(NumRegs,
4239	Builder.getInt8((isI64 \|\| (isF64 && IsSoftFloatABI)) ? 2 : 1));
4240	Builder.CreateStore(NumRegs, NumRegsAddr);
4241
4242	CGF.EmitBranch(Cont);
4243	}
4244
4245	// Case 2: consume space in the overflow area.
4246	Address MemAddr = Address::invalid();
4247	{
4248	CGF.EmitBlock(UsingOverflow);
4249
4250	Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4251
4252	// Everything in the overflow area is rounded up to a size of at least 4.
4253	CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4254
4255	CharUnits Size;
4256	if (!isIndirect) {
4257	auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4258	Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4259	} else {
4260	Size = CGF.getPointerSize();
4261	}
4262
4263	Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4264	Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4265	OverflowAreaAlign);
4266	// Round up address of argument to alignment
4267	CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4268	if (Align > OverflowAreaAlign) {
4269	llvm::Value *Ptr = OverflowArea.getPointer();
4270	OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4271	Align);
4272	}
4273
4274	MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4275
4276	// Increase the overflow area.
4277	OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4278	Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4279	CGF.EmitBranch(Cont);
4280	}
4281
4282	CGF.EmitBlock(Cont);
4283
4284	// Merge the cases with a phi.
4285	Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4286	"vaarg.addr");
4287
4288	// Load the pointer if the argument was passed indirectly.
4289	if (isIndirect) {
4290	Result = Address(Builder.CreateLoad(Result, "aggr"),
4291	getContext().getTypeAlignInChars(Ty));
4292	}
4293
4294	return Result;
4295	}
4296
4297	bool
4298	PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4299	llvm::Value *Address) const {
4300	// This is calculated from the LLVM and GCC tables and verified
4301	// against gcc output. AFAIK all ABIs use the same encoding.
4302
4303	CodeGen::CGBuilderTy &Builder = CGF.Builder;
4304
4305	llvm::IntegerType *i8 = CGF.Int8Ty;
4306	llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4307	llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4308	llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4309
4310	// 0-31: r0-31, the 4-byte general-purpose registers
4311	AssignToArrayRange(Builder, Address, Four8, 0, 31);
4312
4313	// 32-63: fp0-31, the 8-byte floating-point registers
4314	AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4315
4316	// 64-76 are various 4-byte special-purpose registers:
4317	// 64: mq
4318	// 65: lr
4319	// 66: ctr
4320	// 67: ap
4321	// 68-75 cr0-7
4322	// 76: xer
4323	AssignToArrayRange(Builder, Address, Four8, 64, 76);
4324
4325	// 77-108: v0-31, the 16-byte vector registers
4326	AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4327
4328	// 109: vrsave
4329	// 110: vscr
4330	// 111: spe_acc
4331	// 112: spefscr
4332	// 113: sfp
4333	AssignToArrayRange(Builder, Address, Four8, 109, 113);
4334
4335	return false;
4336	}
4337
4338	// PowerPC-64
4339
4340	namespace {
4341	/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4342	class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4343	public:
4344	enum ABIKind {
4345	ELFv1 = 0,
4346	ELFv2
4347	};
4348
4349	private:
4350	static const unsigned GPRBits = 64;
4351	ABIKind Kind;
4352	bool HasQPX;
4353	bool IsSoftFloatABI;
4354
4355	// A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4356	// will be passed in a QPX register.
4357	bool IsQPXVectorTy(const Type *Ty) const {
4358	if (!HasQPX)
4359	return false;
4360
4361	if (const VectorType *VT = Ty->getAs<VectorType>()) {
4362	unsigned NumElements = VT->getNumElements();
4363	if (NumElements == 1)
4364	return false;
4365
4366	if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4367	if (getContext().getTypeSize(Ty) <= 256)
4368	return true;
4369	} else if (VT->getElementType()->
4370	isSpecificBuiltinType(BuiltinType::Float)) {
4371	if (getContext().getTypeSize(Ty) <= 128)
4372	return true;
4373	}
4374	}
4375
4376	return false;
4377	}
4378
4379	bool IsQPXVectorTy(QualType Ty) const {
4380	return IsQPXVectorTy(Ty.getTypePtr());
4381	}
4382
4383	public:
4384	PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4385	bool SoftFloatABI)
4386	: SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4387	IsSoftFloatABI(SoftFloatABI) {}
4388
4389	bool isPromotableTypeForABI(QualType Ty) const;
4390	CharUnits getParamTypeAlignment(QualType Ty) const;
4391
4392	ABIArgInfo classifyReturnType(QualType RetTy) const;
4393	ABIArgInfo classifyArgumentType(QualType Ty) const;
4394
4395	bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4396	bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4397	uint64_t Members) const override;
4398
4399	// TODO: We can add more logic to computeInfo to improve performance.
4400	// Example: For aggregate arguments that fit in a register, we could
4401	// use getDirectInReg (as is done below for structs containing a single
4402	// floating-point value) to avoid pushing them to memory on function
4403	// entry. This would require changing the logic in PPCISelLowering
4404	// when lowering the parameters in the caller and args in the callee.
4405	void computeInfo(CGFunctionInfo &FI) const override {
4406	if (!getCXXABI().classifyReturnType(FI))
4407	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4408	for (auto &I : FI.arguments()) {
4409	// We rely on the default argument classification for the most part.
4410	// One exception: An aggregate containing a single floating-point
4411	// or vector item must be passed in a register if one is available.
4412	const Type *T = isSingleElementStruct(I.type, getContext());
4413	if (T) {
4414	const BuiltinType *BT = T->getAs<BuiltinType>();
4415	if (IsQPXVectorTy(T) \|\|
4416	(T->isVectorType() && getContext().getTypeSize(T) == 128) \|\|
4417	(BT && BT->isFloatingPoint())) {
4418	QualType QT(T, 0);
4419	I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4420	continue;
4421	}
4422	}
4423	I.info = classifyArgumentType(I.type);
4424	}
4425	}
4426
4427	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4428	QualType Ty) const override;
4429
4430	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4431	bool asReturnValue) const override {
4432	return occupiesMoreThan(CGT, scalars, /total/ 4);
4433	}
4434
4435	bool isSwiftErrorInRegister() const override {
4436	return false;
4437	}
4438	};
4439
4440	class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4441
4442	public:
4443	PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4444	PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4445	bool SoftFloatABI)
4446	: TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4447	SoftFloatABI)) {}
4448
4449	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4450	// This is recovered from gcc output.
4451	return 1; // r1 is the dedicated stack pointer
4452	}
4453
4454	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4455	llvm::Value *Address) const override;
4456	};
4457
4458	class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4459	public:
4460	PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4461
4462	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4463	// This is recovered from gcc output.
4464	return 1; // r1 is the dedicated stack pointer
4465	}
4466
4467	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4468	llvm::Value *Address) const override;
4469	};
4470
4471	}
4472
4473	// Return true if the ABI requires Ty to be passed sign- or zero-
4474	// extended to 64 bits.
4475	bool
4476	PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4477	// Treat an enum type as its underlying type.
4478	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4479	Ty = EnumTy->getDecl()->getIntegerType();
4480
4481	// Promotable integer types are required to be promoted by the ABI.
4482	if (Ty->isPromotableIntegerType())
4483	return true;
4484
4485	// In addition to the usual promotable integer types, we also need to
4486	// extend all 32-bit types, since the ABI requires promotion to 64 bits.
4487	if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4488	switch (BT->getKind()) {
4489	case BuiltinType::Int:
4490	case BuiltinType::UInt:
4491	return true;
4492	default:
4493	break;
4494	}
4495
4496	return false;
4497	}
4498
4499	/// isAlignedParamType - Determine whether a type requires 16-byte or
4500	/// higher alignment in the parameter area. Always returns at least 8.
4501	CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4502	// Complex types are passed just like their elements.
4503	if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4504	Ty = CTy->getElementType();
4505
4506	// Only vector types of size 16 bytes need alignment (larger types are
4507	// passed via reference, smaller types are not aligned).
4508	if (IsQPXVectorTy(Ty)) {
4509	if (getContext().getTypeSize(Ty) > 128)
4510	return CharUnits::fromQuantity(32);
4511
4512	return CharUnits::fromQuantity(16);
4513	} else if (Ty->isVectorType()) {
4514	return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4515	}
4516
4517	// For single-element float/vector structs, we consider the whole type
4518	// to have the same alignment requirements as its single element.
4519	const Type *AlignAsType = nullptr;
4520	const Type *EltType = isSingleElementStruct(Ty, getContext());
4521	if (EltType) {
4522	const BuiltinType *BT = EltType->getAs<BuiltinType>();
4523	if (IsQPXVectorTy(EltType) \|\| (EltType->isVectorType() &&
4524	getContext().getTypeSize(EltType) == 128) \|\|
4525	(BT && BT->isFloatingPoint()))
4526	AlignAsType = EltType;
4527	}
4528
4529	// Likewise for ELFv2 homogeneous aggregates.
4530	const Type *Base = nullptr;
4531	uint64_t Members = 0;
4532	if (!AlignAsType && Kind == ELFv2 &&
4533	isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4534	AlignAsType = Base;
4535
4536	// With special case aggregates, only vector base types need alignment.
4537	if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4538	if (getContext().getTypeSize(AlignAsType) > 128)
4539	return CharUnits::fromQuantity(32);
4540
4541	return CharUnits::fromQuantity(16);
4542	} else if (AlignAsType) {
4543	return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4544	}
4545
4546	// Otherwise, we only need alignment for any aggregate type that
4547	// has an alignment requirement of >= 16 bytes.
4548	if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4549	if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4550	return CharUnits::fromQuantity(32);
4551	return CharUnits::fromQuantity(16);
4552	}
4553
4554	return CharUnits::fromQuantity(8);
4555	}
4556
4557	/// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4558	/// aggregate. Base is set to the base element type, and Members is set
4559	/// to the number of base elements.
4560	bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4561	uint64_t &Members) const {
4562	if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4563	uint64_t NElements = AT->getSize().getZExtValue();
4564	if (NElements == 0)
4565	return false;
4566	if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4567	return false;
4568	Members *= NElements;
4569	} else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4570	const RecordDecl *RD = RT->getDecl();
4571	if (RD->hasFlexibleArrayMember())
4572	return false;
4573
4574	Members = 0;
4575
4576	// If this is a C++ record, check the bases first.
4577	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4578	for (const auto &I : CXXRD->bases()) {
4579	// Ignore empty records.
4580	if (isEmptyRecord(getContext(), I.getType(), true))
4581	continue;
4582
4583	uint64_t FldMembers;
4584	if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4585	return false;
4586
4587	Members += FldMembers;
4588	}
4589	}
4590
4591	for (const auto *FD : RD->fields()) {
4592	// Ignore (non-zero arrays of) empty records.
4593	QualType FT = FD->getType();
4594	while (const ConstantArrayType *AT =
4595	getContext().getAsConstantArrayType(FT)) {
4596	if (AT->getSize().getZExtValue() == 0)
4597	return false;
4598	FT = AT->getElementType();
4599	}
4600	if (isEmptyRecord(getContext(), FT, true))
4601	continue;
4602
4603	// For compatibility with GCC, ignore empty bitfields in C++ mode.
4604	if (getContext().getLangOpts().CPlusPlus &&
4605	FD->isZeroLengthBitField(getContext()))
4606	continue;
4607
4608	uint64_t FldMembers;
4609	if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4610	return false;
4611
4612	Members = (RD->isUnion() ?
4613	std::max(Members, FldMembers) : Members + FldMembers);
4614	}
4615
4616	if (!Base)
4617	return false;
4618
4619	// Ensure there is no padding.
4620	if (getContext().getTypeSize(Base) * Members !=
4621	getContext().getTypeSize(Ty))
4622	return false;
4623	} else {
4624	Members = 1;
4625	if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4626	Members = 2;
4627	Ty = CT->getElementType();
4628	}
4629
4630	// Most ABIs only support float, double, and some vector type widths.
4631	if (!isHomogeneousAggregateBaseType(Ty))
4632	return false;
4633
4634	// The base type must be the same for all members. Types that
4635	// agree in both total size and mode (float vs. vector) are
4636	// treated as being equivalent here.
4637	const Type *TyPtr = Ty.getTypePtr();
4638	if (!Base) {
4639	Base = TyPtr;
4640	// If it's a non-power-of-2 vector, its size is already a power-of-2,
4641	// so make sure to widen it explicitly.
4642	if (const VectorType *VT = Base->getAs<VectorType>()) {
4643	QualType EltTy = VT->getElementType();
4644	unsigned NumElements =
4645	getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4646	Base = getContext()
4647	.getVectorType(EltTy, NumElements, VT->getVectorKind())
4648	.getTypePtr();
4649	}
4650	}
4651
4652	if (Base->isVectorType() != TyPtr->isVectorType() \|\|
4653	getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4654	return false;
4655	}
4656	return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4657	}
4658
4659	bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4660	// Homogeneous aggregates for ELFv2 must have base types of float,
4661	// double, long double, or 128-bit vectors.
4662	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4663	if (BT->getKind() == BuiltinType::Float \|\|
4664	BT->getKind() == BuiltinType::Double \|\|
4665	BT->getKind() == BuiltinType::LongDouble \|\|
4666	(getContext().getTargetInfo().hasFloat128Type() &&
4667	(BT->getKind() == BuiltinType::Float128))) {
4668	if (IsSoftFloatABI)
4669	return false;
4670	return true;
4671	}
4672	}
4673	if (const VectorType *VT = Ty->getAs<VectorType>()) {
4674	if (getContext().getTypeSize(VT) == 128 \|\| IsQPXVectorTy(Ty))
4675	return true;
4676	}
4677	return false;
4678	}
4679
4680	bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4681	const Type *Base, uint64_t Members) const {
4682	// Vector and fp128 types require one register, other floating point types
4683	// require one or two registers depending on their size.
4684	uint32_t NumRegs =
4685	((getContext().getTargetInfo().hasFloat128Type() &&
4686	Base->isFloat128Type()) \|\|
4687	Base->isVectorType()) ? 1
4688	: (getContext().getTypeSize(Base) + 63) / 64;
4689
4690	// Homogeneous Aggregates may occupy at most 8 registers.
4691	return Members * NumRegs <= 8;
4692	}
4693
4694	ABIArgInfo
4695	PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
4696	Ty = useFirstFieldIfTransparentUnion(Ty);
4697
4698	if (Ty->isAnyComplexType())
4699	return ABIArgInfo::getDirect();
4700
4701	// Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4702	// or via reference (larger than 16 bytes).
4703	if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4704	uint64_t Size = getContext().getTypeSize(Ty);
4705	if (Size > 128)
4706	return getNaturalAlignIndirect(Ty, /ByVal=/false);
4707	else if (Size < 128) {
4708	llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4709	return ABIArgInfo::getDirect(CoerceTy);
4710	}
4711	}
4712
4713	if (isAggregateTypeForABI(Ty)) {
4714	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4715	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4716
4717	uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4718	uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4719
4720	// ELFv2 homogeneous aggregates are passed as array types.
4721	const Type *Base = nullptr;
4722	uint64_t Members = 0;
4723	if (Kind == ELFv2 &&
4724	isHomogeneousAggregate(Ty, Base, Members)) {
4725	llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4726	llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4727	return ABIArgInfo::getDirect(CoerceTy);
4728	}
4729
4730	// If an aggregate may end up fully in registers, we do not
4731	// use the ByVal method, but pass the aggregate as array.
4732	// This is usually beneficial since we avoid forcing the
4733	// back-end to store the argument to memory.
4734	uint64_t Bits = getContext().getTypeSize(Ty);
4735	if (Bits > 0 && Bits <= 8 * GPRBits) {
4736	llvm::Type *CoerceTy;
4737
4738	// Types up to 8 bytes are passed as integer type (which will be
4739	// properly aligned in the argument save area doubleword).
4740	if (Bits <= GPRBits)
4741	CoerceTy =
4742	llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4743	// Larger types are passed as arrays, with the base type selected
4744	// according to the required alignment in the save area.
4745	else {
4746	uint64_t RegBits = ABIAlign * 8;
4747	uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4748	llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4749	CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4750	}
4751
4752	return ABIArgInfo::getDirect(CoerceTy);
4753	}
4754
4755	// All other aggregates are passed ByVal.
4756	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
4757	/ByVal=/true,
4758	/Realign=/TyAlign > ABIAlign);
4759	}
4760
4761	return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4762	: ABIArgInfo::getDirect());
4763	}
4764
4765	ABIArgInfo
4766	PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4767	if (RetTy->isVoidType())
4768	return ABIArgInfo::getIgnore();
4769
4770	if (RetTy->isAnyComplexType())
4771	return ABIArgInfo::getDirect();
4772
4773	// Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4774	// or via reference (larger than 16 bytes).
4775	if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4776	uint64_t Size = getContext().getTypeSize(RetTy);
4777	if (Size > 128)
4778	return getNaturalAlignIndirect(RetTy);
4779	else if (Size < 128) {
4780	llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4781	return ABIArgInfo::getDirect(CoerceTy);
4782	}
4783	}
4784
4785	if (isAggregateTypeForABI(RetTy)) {
4786	// ELFv2 homogeneous aggregates are returned as array types.
4787	const Type *Base = nullptr;
4788	uint64_t Members = 0;
4789	if (Kind == ELFv2 &&
4790	isHomogeneousAggregate(RetTy, Base, Members)) {
4791	llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4792	llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4793	return ABIArgInfo::getDirect(CoerceTy);
4794	}
4795
4796	// ELFv2 small aggregates are returned in up to two registers.
4797	uint64_t Bits = getContext().getTypeSize(RetTy);
4798	if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4799	if (Bits == 0)
4800	return ABIArgInfo::getIgnore();
4801
4802	llvm::Type *CoerceTy;
4803	if (Bits > GPRBits) {
4804	CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4805	CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4806	} else
4807	CoerceTy =
4808	llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4809	return ABIArgInfo::getDirect(CoerceTy);
4810	}
4811
4812	// All other aggregates are returned indirectly.
4813	return getNaturalAlignIndirect(RetTy);
4814	}
4815
4816	return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4817	: ABIArgInfo::getDirect());
4818	}
4819
4820	// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4821	Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4822	QualType Ty) const {
4823	auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4824	TypeInfo.second = getParamTypeAlignment(Ty);
4825
4826	CharUnits SlotSize = CharUnits::fromQuantity(8);
4827
4828	// If we have a complex type and the base type is smaller than 8 bytes,
4829	// the ABI calls for the real and imaginary parts to be right-adjusted
4830	// in separate doublewords. However, Clang expects us to produce a
4831	// pointer to a structure with the two parts packed tightly. So generate
4832	// loads of the real and imaginary parts relative to the va_list pointer,
4833	// and store them to a temporary structure.
4834	if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4835	CharUnits EltSize = TypeInfo.first / 2;
4836	if (EltSize < SlotSize) {
4837	Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4838	SlotSize * 2, SlotSize,
4839	SlotSize, /AllowHigher/ true);
4840
4841	Address RealAddr = Addr;
4842	Address ImagAddr = RealAddr;
4843	if (CGF.CGM.getDataLayout().isBigEndian()) {
4844	RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4845	SlotSize - EltSize);
4846	ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4847	2 * SlotSize - EltSize);
4848	} else {
4849	ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4850	}
4851
4852	llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4853	RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4854	ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4855	llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4856	llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4857
4858	Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4859	CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4860	/init/ true);
4861	return Temp;
4862	}
4863	}
4864
4865	// Otherwise, just use the general rule.
4866	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /Indirect/ false,
4867	TypeInfo, SlotSize, /AllowHigher/ true);
4868	}
4869
4870	static bool
4871	PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4872	llvm::Value *Address) {
4873	// This is calculated from the LLVM and GCC tables and verified
4874	// against gcc output. AFAIK all ABIs use the same encoding.
4875
4876	CodeGen::CGBuilderTy &Builder = CGF.Builder;
4877
4878	llvm::IntegerType *i8 = CGF.Int8Ty;
4879	llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4880	llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4881	llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4882
4883	// 0-31: r0-31, the 8-byte general-purpose registers
4884	AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4885
4886	// 32-63: fp0-31, the 8-byte floating-point registers
4887	AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4888
4889	// 64-67 are various 8-byte special-purpose registers:
4890	// 64: mq
4891	// 65: lr
4892	// 66: ctr
4893	// 67: ap
4894	AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4895
4896	// 68-76 are various 4-byte special-purpose registers:
4897	// 68-75 cr0-7
4898	// 76: xer
4899	AssignToArrayRange(Builder, Address, Four8, 68, 76);
4900
4901	// 77-108: v0-31, the 16-byte vector registers
4902	AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4903
4904	// 109: vrsave
4905	// 110: vscr
4906	// 111: spe_acc
4907	// 112: spefscr
4908	// 113: sfp
4909	// 114: tfhar
4910	// 115: tfiar
4911	// 116: texasr
4912	AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4913
4914	return false;
4915	}
4916
4917	bool
4918	PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4919	CodeGen::CodeGenFunction &CGF,
4920	llvm::Value *Address) const {
4921
4922	return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4923	}
4924
4925	bool
4926	PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4927	llvm::Value *Address) const {
4928
4929	return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4930	}
4931
4932	//===----------------------------------------------------------------------===//
4933	// AArch64 ABI Implementation
4934	//===----------------------------------------------------------------------===//
4935
4936	namespace {
4937
4938	class AArch64ABIInfo : public SwiftABIInfo {
4939	public:
4940	enum ABIKind {
4941	AAPCS = 0,
4942	DarwinPCS,
4943	Win64
4944	};
4945
4946	private:
4947	ABIKind Kind;
4948
4949	public:
4950	AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4951	: SwiftABIInfo(CGT), Kind(Kind) {}
4952
4953	private:
4954	ABIKind getABIKind() const { return Kind; }
4955	bool isDarwinPCS() const { return Kind == DarwinPCS; }
4956
4957	ABIArgInfo classifyReturnType(QualType RetTy) const;
4958	ABIArgInfo classifyArgumentType(QualType RetTy) const;
4959	bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4960	bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4961	uint64_t Members) const override;
4962
4963	bool isIllegalVectorType(QualType Ty) const;
4964
4965	void computeInfo(CGFunctionInfo &FI) const override {
4966	if (!::classifyReturnType(getCXXABI(), FI, *this))
4967	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4968
4969	for (auto &it : FI.arguments())
4970	it.info = classifyArgumentType(it.type);
4971	}
4972
4973	Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4974	CodeGenFunction &CGF) const;
4975
4976	Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4977	CodeGenFunction &CGF) const;
4978
4979	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4980	QualType Ty) const override {
4981	return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4982	: isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4983	: EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4984	}
4985
4986	Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4987	QualType Ty) const override;
4988
4989	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4990	bool asReturnValue) const override {
4991	return occupiesMoreThan(CGT, scalars, /total/ 4);
4992	}
4993	bool isSwiftErrorInRegister() const override {
4994	return true;
4995	}
4996
4997	bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4998	unsigned elts) const override;
4999	};
5000
5001	class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
5002	public:
5003	AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
5004	: TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
5005
5006	StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5007	return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
5008	}
5009
5010	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5011	return 31;
5012	}
5013
5014	bool doesReturnSlotInterfereWithArgs() const override { return false; }
5015
5016	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
5017	CodeGen::CodeGenModule &CGM) const override {
5018	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5019	if (!FD)
5020	return;
5021	llvm::Function *Fn = cast<llvm::Function>(GV);
5022
5023	auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
5024	if (Kind != CodeGenOptions::SignReturnAddressScope::None) {
5025	Fn->addFnAttr("sign-return-address",
5026	Kind == CodeGenOptions::SignReturnAddressScope::All
5027	? "all"
5028	: "non-leaf");
5029
5030	auto Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
5031	Fn->addFnAttr("sign-return-address-key",
5032	Key == CodeGenOptions::SignReturnAddressKeyValue::AKey
5033	? "a_key"
5034	: "b_key");
5035	}
5036
5037	if (CGM.getCodeGenOpts().BranchTargetEnforcement)
5038	Fn->addFnAttr("branch-target-enforcement");
5039	}
5040	};
5041
5042	class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5043	public:
5044	WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
5045	: AArch64TargetCodeGenInfo(CGT, K) {}
5046
5047	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
5048	CodeGen::CodeGenModule &CGM) const override;
5049
5050	void getDependentLibraryOption(llvm::StringRef Lib,
5051	llvm::SmallString<24> &Opt) const override {
5052	Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5053	}
5054
5055	void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5056	llvm::SmallString<32> &Opt) const override {
5057	Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5058	}
5059	};
5060
5061	void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
5062	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &CGM) const {
5063	AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5064	if (GV->isDeclaration())
5065	return;
5066	addStackProbeTargetAttributes(D, GV, CGM);
5067	}
5068	}
5069
5070	ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const {
5071	Ty = useFirstFieldIfTransparentUnion(Ty);
5072
5073	// Handle illegal vector types here.
5074	if (isIllegalVectorType(Ty)) {
5075	uint64_t Size = getContext().getTypeSize(Ty);
5076	// Android promotes <2 x i8> to i16, not i32
5077	if (isAndroid() && (Size <= 16)) {
5078	llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5079	return ABIArgInfo::getDirect(ResType);
5080	}
5081	if (Size <= 32) {
5082	llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5083	return ABIArgInfo::getDirect(ResType);
5084	}
5085	if (Size == 64) {
5086	llvm::Type *ResType =
5087	llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5088	return ABIArgInfo::getDirect(ResType);
5089	}
5090	if (Size == 128) {
5091	llvm::Type *ResType =
5092	llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5093	return ABIArgInfo::getDirect(ResType);
5094	}
5095	return getNaturalAlignIndirect(Ty, /ByVal=/false);
5096	}
5097
5098	if (!isAggregateTypeForABI(Ty)) {
5099	// Treat an enum type as its underlying type.
5100	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5101	Ty = EnumTy->getDecl()->getIntegerType();
5102
5103	return (Ty->isPromotableIntegerType() && isDarwinPCS()
5104	? ABIArgInfo::getExtend(Ty)
5105	: ABIArgInfo::getDirect());
5106	}
5107
5108	// Structures with either a non-trivial destructor or a non-trivial
5109	// copy constructor are always indirect.
5110	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5111	return getNaturalAlignIndirect(Ty, /ByVal=/RAA ==
5112	CGCXXABI::RAA_DirectInMemory);
5113	}
5114
5115	// Empty records are always ignored on Darwin, but actually passed in C++ mode
5116	// elsewhere for GNU compatibility.
5117	uint64_t Size = getContext().getTypeSize(Ty);
5118	bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5119	if (IsEmpty \|\| Size == 0) {
5120	if (!getContext().getLangOpts().CPlusPlus \|\| isDarwinPCS())
5121	return ABIArgInfo::getIgnore();
5122
5123	// GNU C mode. The only argument that gets ignored is an empty one with size
5124	// 0.
5125	if (IsEmpty && Size == 0)
5126	return ABIArgInfo::getIgnore();
5127	return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5128	}
5129
5130	// Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5131	const Type *Base = nullptr;
5132	uint64_t Members = 0;
5133	if (isHomogeneousAggregate(Ty, Base, Members)) {
5134	return ABIArgInfo::getDirect(
5135	llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5136	}
5137
5138	// Aggregates <= 16 bytes are passed directly in registers or on the stack.
5139	if (Size <= 128) {
5140	// On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5141	// same size and alignment.
5142	if (getTarget().isRenderScriptTarget()) {
5143	return coerceToIntArray(Ty, getContext(), getVMContext());
5144	}
5145	unsigned Alignment;
5146	if (Kind == AArch64ABIInfo::AAPCS) {
5147	Alignment = getContext().getTypeUnadjustedAlign(Ty);
5148	Alignment = Alignment < 128 ? 64 : 128;
5149	} else {
5150	Alignment = getContext().getTypeAlign(Ty);
5151	}
5152	Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5153
5154	// We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5155	// For aggregates with 16-byte alignment, we use i128.
5156	if (Alignment < 128 && Size == 128) {
5157	llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5158	return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5159	}
5160	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5161	}
5162
5163	return getNaturalAlignIndirect(Ty, /ByVal=/false);
5164	}
5165
5166	ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy) const {
5167	if (RetTy->isVoidType())
5168	return ABIArgInfo::getIgnore();
5169
5170	// Large vector types should be returned via memory.
5171	if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5172	return getNaturalAlignIndirect(RetTy);
5173
5174	if (!isAggregateTypeForABI(RetTy)) {
5175	// Treat an enum type as its underlying type.
5176	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5177	RetTy = EnumTy->getDecl()->getIntegerType();
5178
5179	return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5180	? ABIArgInfo::getExtend(RetTy)
5181	: ABIArgInfo::getDirect());
5182	}
5183
5184	uint64_t Size = getContext().getTypeSize(RetTy);
5185	if (isEmptyRecord(getContext(), RetTy, true) \|\| Size == 0)
5186	return ABIArgInfo::getIgnore();
5187
5188	const Type *Base = nullptr;
5189	uint64_t Members = 0;
5190	if (isHomogeneousAggregate(RetTy, Base, Members))
5191	// Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5192	return ABIArgInfo::getDirect();
5193
5194	// Aggregates <= 16 bytes are returned directly in registers or on the stack.
5195	if (Size <= 128) {
5196	// On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5197	// same size and alignment.
5198	if (getTarget().isRenderScriptTarget()) {
5199	return coerceToIntArray(RetTy, getContext(), getVMContext());
5200	}
5201	unsigned Alignment = getContext().getTypeAlign(RetTy);
5202	Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5203
5204	// We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5205	// For aggregates with 16-byte alignment, we use i128.
5206	if (Alignment < 128 && Size == 128) {
5207	llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5208	return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5209	}
5210	return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5211	}
5212
5213	return getNaturalAlignIndirect(RetTy);
5214	}
5215
5216	/// isIllegalVectorType - check whether the vector type is legal for AArch64.
5217	bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5218	if (const VectorType *VT = Ty->getAs<VectorType>()) {
5219	// Check whether VT is legal.
5220	unsigned NumElements = VT->getNumElements();
5221	uint64_t Size = getContext().getTypeSize(VT);
5222	// NumElements should be power of 2.
5223	if (!llvm::isPowerOf2_32(NumElements))
5224	return true;
5225	return Size != 64 && (Size != 128 \|\| NumElements == 1);
5226	}
5227	return false;
5228	}
5229
5230	bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5231	llvm::Type *eltTy,
5232	unsigned elts) const {
5233	if (!llvm::isPowerOf2_32(elts))
5234	return false;
5235	if (totalSize.getQuantity() != 8 &&
5236	(totalSize.getQuantity() != 16 \|\| elts == 1))
5237	return false;
5238	return true;
5239	}
5240
5241	bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5242	// Homogeneous aggregates for AAPCS64 must have base types of a floating
5243	// point type or a short-vector type. This is the same as the 32-bit ABI,
5244	// but with the difference that any floating-point type is allowed,
5245	// including __fp16.
5246	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5247	if (BT->isFloatingPoint())
5248	return true;
5249	} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5250	unsigned VecSize = getContext().getTypeSize(VT);
5251	if (VecSize == 64 \|\| VecSize == 128)
5252	return true;
5253	}
5254	return false;
5255	}
5256
5257	bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5258	uint64_t Members) const {
5259	return Members <= 4;
5260	}
5261
5262	Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5263	QualType Ty,
5264	CodeGenFunction &CGF) const {
5265	ABIArgInfo AI = classifyArgumentType(Ty);
5266	bool IsIndirect = AI.isIndirect();
5267
5268	llvm::Type *BaseTy = CGF.ConvertType(Ty);
5269	if (IsIndirect)
5270	BaseTy = llvm::PointerType::getUnqual(BaseTy);
5271	else if (AI.getCoerceToType())
5272	BaseTy = AI.getCoerceToType();
5273
5274	unsigned NumRegs = 1;
5275	if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5276	BaseTy = ArrTy->getElementType();
5277	NumRegs = ArrTy->getNumElements();
5278	}
5279	bool IsFPR = BaseTy->isFloatingPointTy() \|\| BaseTy->isVectorTy();
5280
5281	// The AArch64 va_list type and handling is specified in the Procedure Call
5282	// Standard, section B.4:
5283	//
5284	// struct {
5285	// void *__stack;
5286	// void *__gr_top;
5287	// void *__vr_top;
5288	// int __gr_offs;
5289	// int __vr_offs;
5290	// };
5291
5292	llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5293	llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5294	llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5295	llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5296
5297	auto TyInfo = getContext().getTypeInfoInChars(Ty);
5298	CharUnits TyAlign = TyInfo.second;
5299
5300	Address reg_offs_p = Address::invalid();
5301	llvm::Value *reg_offs = nullptr;
5302	int reg_top_index;
5303	int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5304	if (!IsFPR) {
5305	// 3 is the field number of __gr_offs
5306	reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p");
5307	reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5308	reg_top_index = 1; // field number for __gr_top
5309	RegSize = llvm::alignTo(RegSize, 8);
5310	} else {
5311	// 4 is the field number of __vr_offs.
5312	reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p");
5313	reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5314	reg_top_index = 2; // field number for __vr_top
5315	RegSize = 16 * NumRegs;
5316	}
5317
5318	//=======================================
5319	// Find out where argument was passed
5320	//=======================================
5321
5322	// If reg_offs >= 0 we're already using the stack for this type of
5323	// argument. We don't want to keep updating reg_offs (in case it overflows,
5324	// though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5325	// whatever they get).
5326	llvm::Value *UsingStack = nullptr;
5327	UsingStack = CGF.Builder.CreateICmpSGE(
5328	reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5329
5330	CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5331
5332	// Otherwise, at least some kind of argument could go in these registers, the
5333	// question is whether this particular type is too big.
5334	CGF.EmitBlock(MaybeRegBlock);
5335
5336	// Integer arguments may need to correct register alignment (for example a
5337	// "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5338	// align __gr_offs to calculate the potential address.
5339	if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5340	int Align = TyAlign.getQuantity();
5341
5342	reg_offs = CGF.Builder.CreateAdd(
5343	reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5344	"align_regoffs");
5345	reg_offs = CGF.Builder.CreateAnd(
5346	reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5347	"aligned_regoffs");
5348	}
5349
5350	// Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5351	// The fact that this is done unconditionally reflects the fact that
5352	// allocating an argument to the stack also uses up all the remaining
5353	// registers of the appropriate kind.
5354	llvm::Value *NewOffset = nullptr;
5355	NewOffset = CGF.Builder.CreateAdd(
5356	reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5357	CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5358
5359	// Now we're in a position to decide whether this argument really was in
5360	// registers or not.
5361	llvm::Value *InRegs = nullptr;
5362	InRegs = CGF.Builder.CreateICmpSLE(
5363	NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5364
5365	CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5366
5367	//=======================================
5368	// Argument was in registers
5369	//=======================================
5370
5371	// Now we emit the code for if the argument was originally passed in
5372	// registers. First start the appropriate block:
5373	CGF.EmitBlock(InRegBlock);
5374
5375	llvm::Value *reg_top = nullptr;
5376	Address reg_top_p =
5377	CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p");
5378	reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5379	Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5380	CharUnits::fromQuantity(IsFPR ? 16 : 8));
5381	Address RegAddr = Address::invalid();
5382	llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5383
5384	if (IsIndirect) {
5385	// If it's been passed indirectly (actually a struct), whatever we find from
5386	// stored registers or on the stack will actually be a struct **.
5387	MemTy = llvm::PointerType::getUnqual(MemTy);
5388	}
5389
5390	const Type *Base = nullptr;
5391	uint64_t NumMembers = 0;
5392	bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5393	if (IsHFA && NumMembers > 1) {
5394	// Homogeneous aggregates passed in registers will have their elements split
5395	// and stored 16-bytes apart regardless of size (they're notionally in qN,
5396	// qN+1, ...). We reload and store into a temporary local variable
5397	// contiguously.
5398	(0) . __assert_fail ("!IsIndirect && \"Homogeneous aggregates should be passed directly\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 5398, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5399	auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5400	llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5401	llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5402	Address Tmp = CGF.CreateTempAlloca(HFATy,
5403	std::max(TyAlign, BaseTyInfo.second));
5404
5405	// On big-endian platforms, the value will be right-aligned in its slot.
5406	int Offset = 0;
5407	if (CGF.CGM.getDataLayout().isBigEndian() &&
5408	BaseTyInfo.first.getQuantity() < 16)
5409	Offset = 16 - BaseTyInfo.first.getQuantity();
5410
5411	for (unsigned i = 0; i < NumMembers; ++i) {
5412	CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5413	Address LoadAddr =
5414	CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5415	LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5416
5417	Address StoreAddr = CGF.Builder.CreateConstArrayGEP(Tmp, i);
5418
5419	llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5420	CGF.Builder.CreateStore(Elem, StoreAddr);
5421	}
5422
5423	RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5424	} else {
5425	// Otherwise the object is contiguous in memory.
5426
5427	// It might be right-aligned in its slot.
5428	CharUnits SlotSize = BaseAddr.getAlignment();
5429	if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5430	(IsHFA \|\| !isAggregateTypeForABI(Ty)) &&
5431	TyInfo.first < SlotSize) {
5432	CharUnits Offset = SlotSize - TyInfo.first;
5433	BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5434	}
5435
5436	RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5437	}
5438
5439	CGF.EmitBranch(ContBlock);
5440
5441	//=======================================
5442	// Argument was on the stack
5443	//=======================================
5444	CGF.EmitBlock(OnStackBlock);
5445
5446	Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p");
5447	llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5448
5449	// Again, stack arguments may need realignment. In this case both integer and
5450	// floating-point ones might be affected.
5451	if (!IsIndirect && TyAlign.getQuantity() > 8) {
5452	int Align = TyAlign.getQuantity();
5453
5454	OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5455
5456	OnStackPtr = CGF.Builder.CreateAdd(
5457	OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5458	"align_stack");
5459	OnStackPtr = CGF.Builder.CreateAnd(
5460	OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5461	"align_stack");
5462
5463	OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5464	}
5465	Address OnStackAddr(OnStackPtr,
5466	std::max(CharUnits::fromQuantity(8), TyAlign));
5467
5468	// All stack slots are multiples of 8 bytes.
5469	CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5470	CharUnits StackSize;
5471	if (IsIndirect)
5472	StackSize = StackSlotSize;
5473	else
5474	StackSize = TyInfo.first.alignTo(StackSlotSize);
5475
5476	llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5477	llvm::Value *NewStack =
5478	CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5479
5480	// Write the new value of __stack for the next call to va_arg
5481	CGF.Builder.CreateStore(NewStack, stack_p);
5482
5483	if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5484	TyInfo.first < StackSlotSize) {
5485	CharUnits Offset = StackSlotSize - TyInfo.first;
5486	OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5487	}
5488
5489	OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5490
5491	CGF.EmitBranch(ContBlock);
5492
5493	//=======================================
5494	// Tidy up
5495	//=======================================
5496	CGF.EmitBlock(ContBlock);
5497
5498	Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5499	OnStackAddr, OnStackBlock, "vaargs.addr");
5500
5501	if (IsIndirect)
5502	return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5503	TyInfo.second);
5504
5505	return ResAddr;
5506	}
5507
5508	Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5509	CodeGenFunction &CGF) const {
5510	// The backend's lowering doesn't support va_arg for aggregates or
5511	// illegal vector types. Lower VAArg here for these cases and use
5512	// the LLVM va_arg instruction for everything else.
5513	if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5514	return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5515
5516	CharUnits SlotSize = CharUnits::fromQuantity(8);
5517
5518	// Empty records are ignored for parameter passing purposes.
5519	if (isEmptyRecord(getContext(), Ty, true)) {
5520	Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5521	Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5522	return Addr;
5523	}
5524
5525	// The size of the actual thing passed, which might end up just
5526	// being a pointer for indirect types.
5527	auto TyInfo = getContext().getTypeInfoInChars(Ty);
5528
5529	// Arguments bigger than 16 bytes which aren't homogeneous
5530	// aggregates should be passed indirectly.
5531	bool IsIndirect = false;
5532	if (TyInfo.first.getQuantity() > 16) {
5533	const Type *Base = nullptr;
5534	uint64_t Members = 0;
5535	IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5536	}
5537
5538	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5539	TyInfo, SlotSize, /AllowHigherAlign/ true);
5540	}
5541
5542	Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5543	QualType Ty) const {
5544	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /indirect/ false,
5545	CGF.getContext().getTypeInfoInChars(Ty),
5546	CharUnits::fromQuantity(8),
5547	/allowHigherAlign/ false);
5548	}
5549
5550	//===----------------------------------------------------------------------===//
5551	// ARM ABI Implementation
5552	//===----------------------------------------------------------------------===//
5553
5554	namespace {
5555
5556	class ARMABIInfo : public SwiftABIInfo {
5557	public:
5558	enum ABIKind {
5559	APCS = 0,
5560	AAPCS = 1,
5561	AAPCS_VFP = 2,
5562	AAPCS16_VFP = 3,
5563	};
5564
5565	private:
5566	ABIKind Kind;
5567
5568	public:
5569	ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5570	: SwiftABIInfo(CGT), Kind(_Kind) {
5571	setCCs();
5572	}
5573
5574	bool isEABI() const {
5575	switch (getTarget().getTriple().getEnvironment()) {
5576	case llvm::Triple::Android:
5577	case llvm::Triple::EABI:
5578	case llvm::Triple::EABIHF:
5579	case llvm::Triple::GNUEABI:
5580	case llvm::Triple::GNUEABIHF:
5581	case llvm::Triple::MuslEABI:
5582	case llvm::Triple::MuslEABIHF:
5583	return true;
5584	default:
5585	return false;
5586	}
5587	}
5588
5589	bool isEABIHF() const {
5590	switch (getTarget().getTriple().getEnvironment()) {
5591	case llvm::Triple::EABIHF:
5592	case llvm::Triple::GNUEABIHF:
5593	case llvm::Triple::MuslEABIHF:
5594	return true;
5595	default:
5596	return false;
5597	}
5598	}
5599
5600	ABIKind getABIKind() const { return Kind; }
5601
5602	private:
5603	ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic,
5604	unsigned functionCallConv) const;
5605	ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic,
5606	unsigned functionCallConv) const;
5607	ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base,
5608	uint64_t Members) const;
5609	ABIArgInfo coerceIllegalVector(QualType Ty) const;
5610	bool isIllegalVectorType(QualType Ty) const;
5611
5612	bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5613	bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5614	uint64_t Members) const override;
5615
5616	bool isEffectivelyAAPCS_VFP(unsigned callConvention, bool acceptHalf) const;
5617
5618	void computeInfo(CGFunctionInfo &FI) const override;
5619
5620	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5621	QualType Ty) const override;
5622
5623	llvm::CallingConv::ID getLLVMDefaultCC() const;
5624	llvm::CallingConv::ID getABIDefaultCC() const;
5625	void setCCs();
5626
5627	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5628	bool asReturnValue) const override {
5629	return occupiesMoreThan(CGT, scalars, /total/ 4);
5630	}
5631	bool isSwiftErrorInRegister() const override {
5632	return true;
5633	}
5634	bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5635	unsigned elts) const override;
5636	};
5637
5638	class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5639	public:
5640	ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5641	:TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5642
5643	const ARMABIInfo &getABIInfo() const {
5644	return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5645	}
5646
5647	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5648	return 13;
5649	}
5650
5651	StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5652	return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5653	}
5654
5655	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5656	llvm::Value *Address) const override {
5657	llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5658
5659	// 0-15 are the 16 integer registers.
5660	AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5661	return false;
5662	}
5663
5664	unsigned getSizeOfUnwindException() const override {
5665	if (getABIInfo().isEABI()) return 88;
5666	return TargetCodeGenInfo::getSizeOfUnwindException();
5667	}
5668
5669	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
5670	CodeGen::CodeGenModule &CGM) const override {
5671	if (GV->isDeclaration())
5672	return;
5673	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5674	if (!FD)
5675	return;
5676
5677	const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5678	if (!Attr)
5679	return;
5680
5681	const char *Kind;
5682	switch (Attr->getInterrupt()) {
5683	case ARMInterruptAttr::Generic: Kind = ""; break;
5684	case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5685	case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5686	case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5687	case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5688	case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5689	}
5690
5691	llvm::Function *Fn = cast<llvm::Function>(GV);
5692
5693	Fn->addFnAttr("interrupt", Kind);
5694
5695	ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5696	if (ABI == ARMABIInfo::APCS)
5697	return;
5698
5699	// AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5700	// however this is not necessarily true on taking any interrupt. Instruct
5701	// the backend to perform a realignment as part of the function prologue.
5702	llvm::AttrBuilder B;
5703	B.addStackAlignmentAttr(8);
5704	Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5705	}
5706	};
5707
5708	class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5709	public:
5710	WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5711	: ARMTargetCodeGenInfo(CGT, K) {}
5712
5713	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
5714	CodeGen::CodeGenModule &CGM) const override;
5715
5716	void getDependentLibraryOption(llvm::StringRef Lib,
5717	llvm::SmallString<24> &Opt) const override {
5718	Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5719	}
5720
5721	void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5722	llvm::SmallString<32> &Opt) const override {
5723	Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5724	}
5725	};
5726
5727	void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5728	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &CGM) const {
5729	ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5730	if (GV->isDeclaration())
5731	return;
5732	addStackProbeTargetAttributes(D, GV, CGM);
5733	}
5734	}
5735
5736	void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5737	if (!::classifyReturnType(getCXXABI(), FI, *this))
5738	FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), FI.isVariadic(),
5739	FI.getCallingConvention());
5740
5741	for (auto &I : FI.arguments())
5742	I.info = classifyArgumentType(I.type, FI.isVariadic(),
5743	FI.getCallingConvention());
5744
5745
5746	// Always honor user-specified calling convention.
5747	if (FI.getCallingConvention() != llvm::CallingConv::C)
5748	return;
5749
5750	llvm::CallingConv::ID cc = getRuntimeCC();
5751	if (cc != llvm::CallingConv::C)
5752	FI.setEffectiveCallingConvention(cc);
5753	}
5754
5755	/// Return the default calling convention that LLVM will use.
5756	llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5757	// The default calling convention that LLVM will infer.
5758	if (isEABIHF() \|\| getTarget().getTriple().isWatchABI())
5759	return llvm::CallingConv::ARM_AAPCS_VFP;
5760	else if (isEABI())
5761	return llvm::CallingConv::ARM_AAPCS;
5762	else
5763	return llvm::CallingConv::ARM_APCS;
5764	}
5765
5766	/// Return the calling convention that our ABI would like us to use
5767	/// as the C calling convention.
5768	llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5769	switch (getABIKind()) {
5770	case APCS: return llvm::CallingConv::ARM_APCS;
5771	case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5772	case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5773	case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5774	}
5775	llvm_unreachable("bad ABI kind");
5776	}
5777
5778	void ARMABIInfo::setCCs() {
5779	assert(getRuntimeCC() == llvm::CallingConv::C);
5780
5781	// Don't muddy up the IR with a ton of explicit annotations if
5782	// they'd just match what LLVM will infer from the triple.
5783	llvm::CallingConv::ID abiCC = getABIDefaultCC();
5784	if (abiCC != getLLVMDefaultCC())
5785	RuntimeCC = abiCC;
5786	}
5787
5788	ABIArgInfo ARMABIInfo::coerceIllegalVector(QualType Ty) const {
5789	uint64_t Size = getContext().getTypeSize(Ty);
5790	if (Size <= 32) {
5791	llvm::Type *ResType =
5792	llvm::Type::getInt32Ty(getVMContext());
5793	return ABIArgInfo::getDirect(ResType);
5794	}
5795	if (Size == 64 \|\| Size == 128) {
5796	llvm::Type *ResType = llvm::VectorType::get(
5797	llvm::Type::getInt32Ty(getVMContext()), Size / 32);
5798	return ABIArgInfo::getDirect(ResType);
5799	}
5800	return getNaturalAlignIndirect(Ty, /ByVal=/false);
5801	}
5802
5803	ABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty,
5804	const Type *Base,
5805	uint64_t Members) const {
5806	(0) . __assert_fail ("Base && \"Base class should be set for homogeneous aggregate\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 5806, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Base && "Base class should be set for homogeneous aggregate");
5807	// Base can be a floating-point or a vector.
5808	if (const VectorType *VT = Base->getAs<VectorType>()) {
5809	// FP16 vectors should be converted to integer vectors
5810	if (!getTarget().hasLegalHalfType() &&
5811	(VT->getElementType()->isFloat16Type() \|\|
5812	VT->getElementType()->isHalfType())) {
5813	uint64_t Size = getContext().getTypeSize(VT);
5814	llvm::Type *NewVecTy = llvm::VectorType::get(
5815	llvm::Type::getInt32Ty(getVMContext()), Size / 32);
5816	llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members);
5817	return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5818	}
5819	}
5820	return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5821	}
5822
5823	ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic,
5824	unsigned functionCallConv) const {
5825	// 6.1.2.1 The following argument types are VFP CPRCs:
5826	// A single-precision floating-point type (including promoted
5827	// half-precision types); A double-precision floating-point type;
5828	// A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5829	// with a Base Type of a single- or double-precision floating-point type,
5830	// 64-bit containerized vectors or 128-bit containerized vectors with one
5831	// to four Elements.
5832	// Variadic functions should always marshal to the base standard.
5833	bool IsAAPCS_VFP =
5834	!isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ false);
5835
5836	Ty = useFirstFieldIfTransparentUnion(Ty);
5837
5838	// Handle illegal vector types here.
5839	if (isIllegalVectorType(Ty))
5840	return coerceIllegalVector(Ty);
5841
5842	// _Float16 and __fp16 get passed as if it were an int or float, but with
5843	// the top 16 bits unspecified. This is not done for OpenCL as it handles the
5844	// half type natively, and does not need to interwork with AAPCS code.
5845	if ((Ty->isFloat16Type() \|\| Ty->isHalfType()) &&
5846	!getContext().getLangOpts().NativeHalfArgsAndReturns) {
5847	llvm::Type *ResType = IsAAPCS_VFP ?
5848	llvm::Type::getFloatTy(getVMContext()) :
5849	llvm::Type::getInt32Ty(getVMContext());
5850	return ABIArgInfo::getDirect(ResType);
5851	}
5852
5853	if (!isAggregateTypeForABI(Ty)) {
5854	// Treat an enum type as its underlying type.
5855	if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5856	Ty = EnumTy->getDecl()->getIntegerType();
5857	}
5858
5859	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
5860	: ABIArgInfo::getDirect());
5861	}
5862
5863	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5864	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5865	}
5866
5867	// Ignore empty records.
5868	if (isEmptyRecord(getContext(), Ty, true))
5869	return ABIArgInfo::getIgnore();
5870
5871	if (IsAAPCS_VFP) {
5872	// Homogeneous Aggregates need to be expanded when we can fit the aggregate
5873	// into VFP registers.
5874	const Type *Base = nullptr;
5875	uint64_t Members = 0;
5876	if (isHomogeneousAggregate(Ty, Base, Members))
5877	return classifyHomogeneousAggregate(Ty, Base, Members);
5878	} else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5879	// WatchOS does have homogeneous aggregates. Note that we intentionally use
5880	// this convention even for a variadic function: the backend will use GPRs
5881	// if needed.
5882	const Type *Base = nullptr;
5883	uint64_t Members = 0;
5884	if (isHomogeneousAggregate(Ty, Base, Members)) {
5885	(0) . __assert_fail ("Base && Members <= 4 && \"unexpected homogeneous aggregate\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 5885, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5886	llvm::Type *Ty =
5887	llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5888	return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5889	}
5890	}
5891
5892	if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5893	getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5894	// WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5895	// bigger than 128-bits, they get placed in space allocated by the caller,
5896	// and a pointer is passed.
5897	return ABIArgInfo::getIndirect(
5898	CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5899	}
5900
5901	// Support byval for ARM.
5902	// The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5903	// most 8-byte. We realign the indirect argument if type alignment is bigger
5904	// than ABI alignment.
5905	uint64_t ABIAlign = 4;
5906	uint64_t TyAlign;
5907	if (getABIKind() == ARMABIInfo::AAPCS_VFP \|\|
5908	getABIKind() == ARMABIInfo::AAPCS) {
5909	TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
5910	ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5911	} else {
5912	TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
5913	}
5914	if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5915	(0) . __assert_fail ("getABIKind() != ARMABIInfo..AAPCS16_VFP && \"unexpected byval\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 5915, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5916	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
5917	/ByVal=/true,
5918	/Realign=/TyAlign > ABIAlign);
5919	}
5920
5921	// On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5922	// same size and alignment.
5923	if (getTarget().isRenderScriptTarget()) {
5924	return coerceToIntArray(Ty, getContext(), getVMContext());
5925	}
5926
5927	// Otherwise, pass by coercing to a structure of the appropriate size.
5928	llvm::Type* ElemTy;
5929	unsigned SizeRegs;
5930	// FIXME: Try to match the types of the arguments more accurately where
5931	// we can.
5932	if (TyAlign <= 4) {
5933	ElemTy = llvm::Type::getInt32Ty(getVMContext());
5934	SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5935	} else {
5936	ElemTy = llvm::Type::getInt64Ty(getVMContext());
5937	SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5938	}
5939
5940	return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5941	}
5942
5943	static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5944	llvm::LLVMContext &VMContext) {
5945	// APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5946	// is called integer-like if its size is less than or equal to one word, and
5947	// the offset of each of its addressable sub-fields is zero.
5948
5949	uint64_t Size = Context.getTypeSize(Ty);
5950
5951	// Check that the type fits in a word.
5952	if (Size > 32)
5953	return false;
5954
5955	// FIXME: Handle vector types!
5956	if (Ty->isVectorType())
5957	return false;
5958
5959	// Float types are never treated as "integer like".
5960	if (Ty->isRealFloatingType())
5961	return false;
5962
5963	// If this is a builtin or pointer type then it is ok.
5964	if (Ty->getAs<BuiltinType>() \|\| Ty->isPointerType())
5965	return true;
5966
5967	// Small complex integer types are "integer like".
5968	if (const ComplexType *CT = Ty->getAs<ComplexType>())
5969	return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5970
5971	// Single element and zero sized arrays should be allowed, by the definition
5972	// above, but they are not.
5973
5974	// Otherwise, it must be a record type.
5975	const RecordType *RT = Ty->getAs<RecordType>();
5976	if (!RT) return false;
5977
5978	// Ignore records with flexible arrays.
5979	const RecordDecl *RD = RT->getDecl();
5980	if (RD->hasFlexibleArrayMember())
5981	return false;
5982
5983	// Check that all sub-fields are at offset 0, and are themselves "integer
5984	// like".
5985	const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5986
5987	bool HadField = false;
5988	unsigned idx = 0;
5989	for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5990	i != e; ++i, ++idx) {
5991	const FieldDecl FD = i;
5992
5993	// Bit-fields are not addressable, we only need to verify they are "integer
5994	// like". We still have to disallow a subsequent non-bitfield, for example:
5995	// struct { int : 0; int x }
5996	// is non-integer like according to gcc.
5997	if (FD->isBitField()) {
5998	if (!RD->isUnion())
5999	HadField = true;
6000
6001	if (!isIntegerLikeType(FD->getType(), Context, VMContext))
6002	return false;
6003
6004	continue;
6005	}
6006
6007	// Check if this field is at offset 0.
6008	if (Layout.getFieldOffset(idx) != 0)
6009	return false;
6010
6011	if (!isIntegerLikeType(FD->getType(), Context, VMContext))
6012	return false;
6013
6014	// Only allow at most one field in a structure. This doesn't match the
6015	// wording above, but follows gcc in situations with a field following an
6016	// empty structure.
6017	if (!RD->isUnion()) {
6018	if (HadField)
6019	return false;
6020
6021	HadField = true;
6022	}
6023	}
6024
6025	return true;
6026	}
6027
6028	ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy, bool isVariadic,
6029	unsigned functionCallConv) const {
6030
6031	// Variadic functions should always marshal to the base standard.
6032	bool IsAAPCS_VFP =
6033	!isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ true);
6034
6035	if (RetTy->isVoidType())
6036	return ABIArgInfo::getIgnore();
6037
6038	if (const VectorType *VT = RetTy->getAs<VectorType>()) {
6039	// Large vector types should be returned via memory.
6040	if (getContext().getTypeSize(RetTy) > 128)
6041	return getNaturalAlignIndirect(RetTy);
6042	// FP16 vectors should be converted to integer vectors
6043	if (!getTarget().hasLegalHalfType() &&
6044	(VT->getElementType()->isFloat16Type() \|\|
6045	VT->getElementType()->isHalfType()))
6046	return coerceIllegalVector(RetTy);
6047	}
6048
6049	// _Float16 and __fp16 get returned as if it were an int or float, but with
6050	// the top 16 bits unspecified. This is not done for OpenCL as it handles the
6051	// half type natively, and does not need to interwork with AAPCS code.
6052	if ((RetTy->isFloat16Type() \|\| RetTy->isHalfType()) &&
6053	!getContext().getLangOpts().NativeHalfArgsAndReturns) {
6054	llvm::Type *ResType = IsAAPCS_VFP ?
6055	llvm::Type::getFloatTy(getVMContext()) :
6056	llvm::Type::getInt32Ty(getVMContext());
6057	return ABIArgInfo::getDirect(ResType);
6058	}
6059
6060	if (!isAggregateTypeForABI(RetTy)) {
6061	// Treat an enum type as its underlying type.
6062	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6063	RetTy = EnumTy->getDecl()->getIntegerType();
6064
6065	return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6066	: ABIArgInfo::getDirect();
6067	}
6068
6069	// Are we following APCS?
6070	if (getABIKind() == APCS) {
6071	if (isEmptyRecord(getContext(), RetTy, false))
6072	return ABIArgInfo::getIgnore();
6073
6074	// Complex types are all returned as packed integers.
6075	//
6076	// FIXME: Consider using 2 x vector types if the back end handles them
6077	// correctly.
6078	if (RetTy->isAnyComplexType())
6079	return ABIArgInfo::getDirect(llvm::IntegerType::get(
6080	getVMContext(), getContext().getTypeSize(RetTy)));
6081
6082	// Integer like structures are returned in r0.
6083	if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
6084	// Return in the smallest viable integer type.
6085	uint64_t Size = getContext().getTypeSize(RetTy);
6086	if (Size <= 8)
6087	return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6088	if (Size <= 16)
6089	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6090	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6091	}
6092
6093	// Otherwise return in memory.
6094	return getNaturalAlignIndirect(RetTy);
6095	}
6096
6097	// Otherwise this is an AAPCS variant.
6098
6099	if (isEmptyRecord(getContext(), RetTy, true))
6100	return ABIArgInfo::getIgnore();
6101
6102	// Check for homogeneous aggregates with AAPCS-VFP.
6103	if (IsAAPCS_VFP) {
6104	const Type *Base = nullptr;
6105	uint64_t Members = 0;
6106	if (isHomogeneousAggregate(RetTy, Base, Members))
6107	return classifyHomogeneousAggregate(RetTy, Base, Members);
6108	}
6109
6110	// Aggregates <= 4 bytes are returned in r0; other aggregates
6111	// are returned indirectly.
6112	uint64_t Size = getContext().getTypeSize(RetTy);
6113	if (Size <= 32) {
6114	// On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
6115	// same size and alignment.
6116	if (getTarget().isRenderScriptTarget()) {
6117	return coerceToIntArray(RetTy, getContext(), getVMContext());
6118	}
6119	if (getDataLayout().isBigEndian())
6120	// Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
6121	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6122
6123	// Return in the smallest viable integer type.
6124	if (Size <= 8)
6125	return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6126	if (Size <= 16)
6127	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6128	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6129	} else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
6130	llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
6131	llvm::Type *CoerceTy =
6132	llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
6133	return ABIArgInfo::getDirect(CoerceTy);
6134	}
6135
6136	return getNaturalAlignIndirect(RetTy);
6137	}
6138
6139	/// isIllegalVector - check whether Ty is an illegal vector type.
6140	bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
6141	if (const VectorType *VT = Ty->getAs<VectorType> ()) {
6142	// On targets that don't support FP16, FP16 is expanded into float, and we
6143	// don't want the ABI to depend on whether or not FP16 is supported in
6144	// hardware. Thus return false to coerce FP16 vectors into integer vectors.
6145	if (!getTarget().hasLegalHalfType() &&
6146	(VT->getElementType()->isFloat16Type() \|\|
6147	VT->getElementType()->isHalfType()))
6148	return true;
6149	if (isAndroid()) {
6150	// Android shipped using Clang 3.1, which supported a slightly different
6151	// vector ABI. The primary differences were that 3-element vector types
6152	// were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
6153	// accepts that legacy behavior for Android only.
6154	// Check whether VT is legal.
6155	unsigned NumElements = VT->getNumElements();
6156	// NumElements should be power of 2 or equal to 3.
6157	if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
6158	return true;
6159	} else {
6160	// Check whether VT is legal.
6161	unsigned NumElements = VT->getNumElements();
6162	uint64_t Size = getContext().getTypeSize(VT);
6163	// NumElements should be power of 2.
6164	if (!llvm::isPowerOf2_32(NumElements))
6165	return true;
6166	// Size should be greater than 32 bits.
6167	return Size <= 32;
6168	}
6169	}
6170	return false;
6171	}
6172
6173	bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
6174	llvm::Type *eltTy,
6175	unsigned numElts) const {
6176	if (!llvm::isPowerOf2_32(numElts))
6177	return false;
6178	unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
6179	if (size > 64)
6180	return false;
6181	if (vectorSize.getQuantity() != 8 &&
6182	(vectorSize.getQuantity() != 16 \|\| numElts == 1))
6183	return false;
6184	return true;
6185	}
6186
6187	bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
6188	// Homogeneous aggregates for AAPCS-VFP must have base types of float,
6189	// double, or 64-bit or 128-bit vectors.
6190	if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
6191	if (BT->getKind() == BuiltinType::Float \|\|
6192	BT->getKind() == BuiltinType::Double \|\|
6193	BT->getKind() == BuiltinType::LongDouble)
6194	return true;
6195	} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
6196	unsigned VecSize = getContext().getTypeSize(VT);
6197	if (VecSize == 64 \|\| VecSize == 128)
6198	return true;
6199	}
6200	return false;
6201	}
6202
6203	bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
6204	uint64_t Members) const {
6205	return Members <= 4;
6206	}
6207
6208	bool ARMABIInfo::isEffectivelyAAPCS_VFP(unsigned callConvention,
6209	bool acceptHalf) const {
6210	// Give precedence to user-specified calling conventions.
6211	if (callConvention != llvm::CallingConv::C)
6212	return (callConvention == llvm::CallingConv::ARM_AAPCS_VFP);
6213	else
6214	return (getABIKind() == AAPCS_VFP) \|\|
6215	(acceptHalf && (getABIKind() == AAPCS16_VFP));
6216	}
6217
6218	Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6219	QualType Ty) const {
6220	CharUnits SlotSize = CharUnits::fromQuantity(4);
6221
6222	// Empty records are ignored for parameter passing purposes.
6223	if (isEmptyRecord(getContext(), Ty, true)) {
6224	Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
6225	Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
6226	return Addr;
6227	}
6228
6229	auto TyInfo = getContext().getTypeInfoInChars(Ty);
6230	CharUnits TyAlignForABI = TyInfo.second;
6231
6232	// Use indirect if size of the illegal vector is bigger than 16 bytes.
6233	bool IsIndirect = false;
6234	const Type *Base = nullptr;
6235	uint64_t Members = 0;
6236	if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
6237	IsIndirect = true;
6238
6239	// ARMv7k passes structs bigger than 16 bytes indirectly, in space
6240	// allocated by the caller.
6241	} else if (TyInfo.first > CharUnits::fromQuantity(16) &&
6242	getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6243	!isHomogeneousAggregate(Ty, Base, Members)) {
6244	IsIndirect = true;
6245
6246	// Otherwise, bound the type's ABI alignment.
6247	// The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6248	// APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6249	// Our callers should be prepared to handle an under-aligned address.
6250	} else if (getABIKind() == ARMABIInfo::AAPCS_VFP \|\|
6251	getABIKind() == ARMABIInfo::AAPCS) {
6252	TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6253	TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6254	} else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6255	// ARMv7k allows type alignment up to 16 bytes.
6256	TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6257	TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6258	} else {
6259	TyAlignForABI = CharUnits::fromQuantity(4);
6260	}
6261	TyInfo.second = TyAlignForABI;
6262
6263	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6264	SlotSize, /AllowHigherAlign/ true);
6265	}
6266
6267	//===----------------------------------------------------------------------===//
6268	// NVPTX ABI Implementation
6269	//===----------------------------------------------------------------------===//
6270
6271	namespace {
6272
6273	class NVPTXABIInfo : public ABIInfo {
6274	public:
6275	NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6276
6277	ABIArgInfo classifyReturnType(QualType RetTy) const;
6278	ABIArgInfo classifyArgumentType(QualType Ty) const;
6279
6280	void computeInfo(CGFunctionInfo &FI) const override;
6281	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6282	QualType Ty) const override;
6283	};
6284
6285	class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6286	public:
6287	NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6288	: TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6289
6290	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
6291	CodeGen::CodeGenModule &M) const override;
6292	bool shouldEmitStaticExternCAliases() const override;
6293
6294	private:
6295	// Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6296	// resulting MDNode to the nvvm.annotations MDNode.
6297	static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6298	};
6299
6300	/// Checks if the type is unsupported directly by the current target.
6301	static bool isUnsupportedType(ASTContext &Context, QualType T) {
6302	if (!Context.getTargetInfo().hasFloat16Type() && T->isFloat16Type())
6303	return true;
6304	if (!Context.getTargetInfo().hasFloat128Type() && T->isFloat128Type())
6305	return true;
6306	if (!Context.getTargetInfo().hasInt128Type() && T->isIntegerType() &&
6307	Context.getTypeSize(T) > 64)
6308	return true;
6309	if (const auto *AT = T->getAsArrayTypeUnsafe())
6310	return isUnsupportedType(Context, AT->getElementType());
6311	const auto *RT = T->getAs<RecordType>();
6312	if (!RT)
6313	return false;
6314	const RecordDecl *RD = RT->getDecl();
6315
6316	// If this is a C++ record, check the bases first.
6317	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6318	for (const CXXBaseSpecifier &I : CXXRD->bases())
6319	if (isUnsupportedType(Context, I.getType()))
6320	return true;
6321
6322	for (const FieldDecl *I : RD->fields())
6323	if (isUnsupportedType(Context, I->getType()))
6324	return true;
6325	return false;
6326	}
6327
6328	/// Coerce the given type into an array with maximum allowed size of elements.
6329	static ABIArgInfo coerceToIntArrayWithLimit(QualType Ty, ASTContext &Context,
6330	llvm::LLVMContext &LLVMContext,
6331	unsigned MaxSize) {
6332	// Alignment and Size are measured in bits.
6333	const uint64_t Size = Context.getTypeSize(Ty);
6334	const uint64_t Alignment = Context.getTypeAlign(Ty);
6335	const unsigned Div = std::min<unsigned>(MaxSize, Alignment);
6336	llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Div);
6337	const uint64_t NumElements = (Size + Div - 1) / Div;
6338	return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
6339	}
6340
6341	ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
6342	if (RetTy->isVoidType())
6343	return ABIArgInfo::getIgnore();
6344
6345	if (getContext().getLangOpts().OpenMP &&
6346	getContext().getLangOpts().OpenMPIsDevice &&
6347	isUnsupportedType(getContext(), RetTy))
6348	return coerceToIntArrayWithLimit(RetTy, getContext(), getVMContext(), 64);
6349
6350	// note: this is different from default ABI
6351	if (!RetTy->isScalarType())
6352	return ABIArgInfo::getDirect();
6353
6354	// Treat an enum type as its underlying type.
6355	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6356	RetTy = EnumTy->getDecl()->getIntegerType();
6357
6358	return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6359	: ABIArgInfo::getDirect());
6360	}
6361
6362	ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
6363	// Treat an enum type as its underlying type.
6364	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6365	Ty = EnumTy->getDecl()->getIntegerType();
6366
6367	// Return aggregates type as indirect by value
6368	if (isAggregateTypeForABI(Ty))
6369	return getNaturalAlignIndirect(Ty, /* byval */ true);
6370
6371	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
6372	: ABIArgInfo::getDirect());
6373	}
6374
6375	void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6376	if (!getCXXABI().classifyReturnType(FI))
6377	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6378	for (auto &I : FI.arguments())
6379	I.info = classifyArgumentType(I.type);
6380
6381	// Always honor user-specified calling convention.
6382	if (FI.getCallingConvention() != llvm::CallingConv::C)
6383	return;
6384
6385	FI.setEffectiveCallingConvention(getRuntimeCC());
6386	}
6387
6388	Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6389	QualType Ty) const {
6390	llvm_unreachable("NVPTX does not support varargs");
6391	}
6392
6393	void NVPTXTargetCodeGenInfo::setTargetAttributes(
6394	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &M) const {
6395	if (GV->isDeclaration())
6396	return;
6397	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6398	if (!FD) return;
6399
6400	llvm::Function *F = cast<llvm::Function>(GV);
6401
6402	// Perform special handling in OpenCL mode
6403	if (M.getLangOpts().OpenCL) {
6404	// Use OpenCL function attributes to check for kernel functions
6405	// By default, all functions are device functions
6406	if (FD->hasAttr<OpenCLKernelAttr>()) {
6407	// OpenCL __kernel functions get kernel metadata
6408	// Create !{<func-ref>, metadata !"kernel", i32 1} node
6409	addNVVMMetadata(F, "kernel", 1);
6410	// And kernel functions are not subject to inlining
6411	F->addFnAttr(llvm::Attribute::NoInline);
6412	}
6413	}
6414
6415	// Perform special handling in CUDA mode.
6416	if (M.getLangOpts().CUDA) {
6417	// CUDA __global__ functions get a kernel metadata entry. Since
6418	// __global__ functions cannot be called from the device, we do not
6419	// need to set the noinline attribute.
6420	if (FD->hasAttr<CUDAGlobalAttr>()) {
6421	// Create !{<func-ref>, metadata !"kernel", i32 1} node
6422	addNVVMMetadata(F, "kernel", 1);
6423	}
6424	if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6425	// Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6426	llvm::APSInt MaxThreads(32);
6427	MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6428	if (MaxThreads > 0)
6429	addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6430
6431	// min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6432	// not specified in __launch_bounds__ or if the user specified a 0 value,
6433	// we don't have to add a PTX directive.
6434	if (Attr->getMinBlocks()) {
6435	llvm::APSInt MinBlocks(32);
6436	MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6437	if (MinBlocks > 0)
6438	// Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6439	addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6440	}
6441	}
6442	}
6443	}
6444
6445	void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6446	int Operand) {
6447	llvm::Module *M = F->getParent();
6448	llvm::LLVMContext &Ctx = M->getContext();
6449
6450	// Get "nvvm.annotations" metadata node
6451	llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6452
6453	llvm::Metadata *MDVals[] = {
6454	llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6455	llvm::ConstantAsMetadata::get(
6456	llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6457	// Append metadata to nvvm.annotations
6458	MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6459	}
6460
6461	bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
6462	return false;
6463	}
6464	}
6465
6466	//===----------------------------------------------------------------------===//
6467	// SystemZ ABI Implementation
6468	//===----------------------------------------------------------------------===//
6469
6470	namespace {
6471
6472	class SystemZABIInfo : public SwiftABIInfo {
6473	bool HasVector;
6474
6475	public:
6476	SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6477	: SwiftABIInfo(CGT), HasVector(HV) {}
6478
6479	bool isPromotableIntegerType(QualType Ty) const;
6480	bool isCompoundType(QualType Ty) const;
6481	bool isVectorArgumentType(QualType Ty) const;
6482	bool isFPArgumentType(QualType Ty) const;
6483	QualType GetSingleElementType(QualType Ty) const;
6484
6485	ABIArgInfo classifyReturnType(QualType RetTy) const;
6486	ABIArgInfo classifyArgumentType(QualType ArgTy) const;
6487
6488	void computeInfo(CGFunctionInfo &FI) const override {
6489	if (!getCXXABI().classifyReturnType(FI))
6490	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
6491	for (auto &I : FI.arguments())
6492	I.info = classifyArgumentType(I.type);
6493	}
6494
6495	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6496	QualType Ty) const override;
6497
6498	bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
6499	bool asReturnValue) const override {
6500	return occupiesMoreThan(CGT, scalars, /total/ 4);
6501	}
6502	bool isSwiftErrorInRegister() const override {
6503	return false;
6504	}
6505	};
6506
6507	class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6508	public:
6509	SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6510	: TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6511	};
6512
6513	}
6514
6515	bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6516	// Treat an enum type as its underlying type.
6517	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6518	Ty = EnumTy->getDecl()->getIntegerType();
6519
6520	// Promotable integer types are required to be promoted by the ABI.
6521	if (Ty->isPromotableIntegerType())
6522	return true;
6523
6524	// 32-bit values must also be promoted.
6525	if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6526	switch (BT->getKind()) {
6527	case BuiltinType::Int:
6528	case BuiltinType::UInt:
6529	return true;
6530	default:
6531	return false;
6532	}
6533	return false;
6534	}
6535
6536	bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6537	return (Ty->isAnyComplexType() \|\|
6538	Ty->isVectorType() \|\|
6539	isAggregateTypeForABI(Ty));
6540	}
6541
6542	bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6543	return (HasVector &&
6544	Ty->isVectorType() &&
6545	getContext().getTypeSize(Ty) <= 128);
6546	}
6547
6548	bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6549	if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6550	switch (BT->getKind()) {
6551	case BuiltinType::Float:
6552	case BuiltinType::Double:
6553	return true;
6554	default:
6555	return false;
6556	}
6557
6558	return false;
6559	}
6560
6561	QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6562	if (const RecordType *RT = Ty->getAsStructureType()) {
6563	const RecordDecl *RD = RT->getDecl();
6564	QualType Found;
6565
6566	// If this is a C++ record, check the bases first.
6567	if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6568	for (const auto &I : CXXRD->bases()) {
6569	QualType Base = I.getType();
6570
6571	// Empty bases don't affect things either way.
6572	if (isEmptyRecord(getContext(), Base, true))
6573	continue;
6574
6575	if (!Found.isNull())
6576	return Ty;
6577	Found = GetSingleElementType(Base);
6578	}
6579
6580	// Check the fields.
6581	for (const auto *FD : RD->fields()) {
6582	// For compatibility with GCC, ignore empty bitfields in C++ mode.
6583	// Unlike isSingleElementStruct(), empty structure and array fields
6584	// do count. So do anonymous bitfields that aren't zero-sized.
6585	if (getContext().getLangOpts().CPlusPlus &&
6586	FD->isZeroLengthBitField(getContext()))
6587	continue;
6588
6589	// Unlike isSingleElementStruct(), arrays do not count.
6590	// Nested structures still do though.
6591	if (!Found.isNull())
6592	return Ty;
6593	Found = GetSingleElementType(FD->getType());
6594	}
6595
6596	// Unlike isSingleElementStruct(), trailing padding is allowed.
6597	// An 8-byte aligned struct s { float f; } is passed as a double.
6598	if (!Found.isNull())
6599	return Found;
6600	}
6601
6602	return Ty;
6603	}
6604
6605	Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6606	QualType Ty) const {
6607	// Assume that va_list type is correct; should be pointer to LLVM type:
6608	// struct {
6609	// i64 __gpr;
6610	// i64 __fpr;
6611	// i8 *__overflow_arg_area;
6612	// i8 *__reg_save_area;
6613	// };
6614
6615	// Every non-vector argument occupies 8 bytes and is passed by preference
6616	// in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6617	// always passed on the stack.
6618	Ty = getContext().getCanonicalType(Ty);
6619	auto TyInfo = getContext().getTypeInfoInChars(Ty);
6620	llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6621	llvm::Type *DirectTy = ArgTy;
6622	ABIArgInfo AI = classifyArgumentType(Ty);
6623	bool IsIndirect = AI.isIndirect();
6624	bool InFPRs = false;
6625	bool IsVector = false;
6626	CharUnits UnpaddedSize;
6627	CharUnits DirectAlign;
6628	if (IsIndirect) {
6629	DirectTy = llvm::PointerType::getUnqual(DirectTy);
6630	UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6631	} else {
6632	if (AI.getCoerceToType())
6633	ArgTy = AI.getCoerceToType();
6634	InFPRs = ArgTy->isFloatTy() \|\| ArgTy->isDoubleTy();
6635	IsVector = ArgTy->isVectorTy();
6636	UnpaddedSize = TyInfo.first;
6637	DirectAlign = TyInfo.second;
6638	}
6639	CharUnits PaddedSize = CharUnits::fromQuantity(8);
6640	if (IsVector && UnpaddedSize > PaddedSize)
6641	PaddedSize = CharUnits::fromQuantity(16);
6642	(0) . __assert_fail ("(UnpaddedSize <= PaddedSize) && \"Invalid argument size.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 6642, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6643
6644	CharUnits Padding = (PaddedSize - UnpaddedSize);
6645
6646	llvm::Type *IndexTy = CGF.Int64Ty;
6647	llvm::Value *PaddedSizeV =
6648	llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6649
6650	if (IsVector) {
6651	// Work out the address of a vector argument on the stack.
6652	// Vector arguments are always passed in the high bits of a
6653	// single (8 byte) or double (16 byte) stack slot.
6654	Address OverflowArgAreaPtr =
6655	CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr");
6656	Address OverflowArgArea =
6657	Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6658	TyInfo.second);
6659	Address MemAddr =
6660	CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6661
6662	// Update overflow_arg_area_ptr pointer
6663	llvm::Value *NewOverflowArgArea =
6664	CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6665	"overflow_arg_area");
6666	CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6667
6668	return MemAddr;
6669	}
6670
6671	assert(PaddedSize.getQuantity() == 8);
6672
6673	unsigned MaxRegs, RegCountField, RegSaveIndex;
6674	CharUnits RegPadding;
6675	if (InFPRs) {
6676	MaxRegs = 4; // Maximum of 4 FPR arguments
6677	RegCountField = 1; // __fpr
6678	RegSaveIndex = 16; // save offset for f0
6679	RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6680	} else {
6681	MaxRegs = 5; // Maximum of 5 GPR arguments
6682	RegCountField = 0; // __gpr
6683	RegSaveIndex = 2; // save offset for r2
6684	RegPadding = Padding; // values are passed in the low bits of a GPR
6685	}
6686
6687	Address RegCountPtr =
6688	CGF.Builder.CreateStructGEP(VAListAddr, RegCountField, "reg_count_ptr");
6689	llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6690	llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6691	llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6692	"fits_in_regs");
6693
6694	llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6695	llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6696	llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6697	CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6698
6699	// Emit code to load the value if it was passed in registers.
6700	CGF.EmitBlock(InRegBlock);
6701
6702	// Work out the address of an argument register.
6703	llvm::Value *ScaledRegCount =
6704	CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6705	llvm::Value *RegBase =
6706	llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6707	+ RegPadding.getQuantity());
6708	llvm::Value *RegOffset =
6709	CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6710	Address RegSaveAreaPtr =
6711	CGF.Builder.CreateStructGEP(VAListAddr, 3, "reg_save_area_ptr");
6712	llvm::Value *RegSaveArea =
6713	CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6714	Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6715	"raw_reg_addr"),
6716	PaddedSize);
6717	Address RegAddr =
6718	CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6719
6720	// Update the register count
6721	llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6722	llvm::Value *NewRegCount =
6723	CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6724	CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6725	CGF.EmitBranch(ContBlock);
6726
6727	// Emit code to load the value if it was passed in memory.
6728	CGF.EmitBlock(InMemBlock);
6729
6730	// Work out the address of a stack argument.
6731	Address OverflowArgAreaPtr =
6732	CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr");
6733	Address OverflowArgArea =
6734	Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6735	PaddedSize);
6736	Address RawMemAddr =
6737	CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6738	Address MemAddr =
6739	CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6740
6741	// Update overflow_arg_area_ptr pointer
6742	llvm::Value *NewOverflowArgArea =
6743	CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6744	"overflow_arg_area");
6745	CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6746	CGF.EmitBranch(ContBlock);
6747
6748	// Return the appropriate result.
6749	CGF.EmitBlock(ContBlock);
6750	Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6751	MemAddr, InMemBlock, "va_arg.addr");
6752
6753	if (IsIndirect)
6754	ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6755	TyInfo.second);
6756
6757	return ResAddr;
6758	}
6759
6760	ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const {
6761	if (RetTy->isVoidType())
6762	return ABIArgInfo::getIgnore();
6763	if (isVectorArgumentType(RetTy))
6764	return ABIArgInfo::getDirect();
6765	if (isCompoundType(RetTy) \|\| getContext().getTypeSize(RetTy) > 64)
6766	return getNaturalAlignIndirect(RetTy);
6767	return (isPromotableIntegerType(RetTy) ? ABIArgInfo::getExtend(RetTy)
6768	: ABIArgInfo::getDirect());
6769	}
6770
6771	ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
6772	// Handle the generic C++ ABI.
6773	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6774	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6775
6776	// Integers and enums are extended to full register width.
6777	if (isPromotableIntegerType(Ty))
6778	return ABIArgInfo::getExtend(Ty);
6779
6780	// Handle vector types and vector-like structure types. Note that
6781	// as opposed to float-like structure types, we do not allow any
6782	// padding for vector-like structures, so verify the sizes match.
6783	uint64_t Size = getContext().getTypeSize(Ty);
6784	QualType SingleElementTy = GetSingleElementType(Ty);
6785	if (isVectorArgumentType(SingleElementTy) &&
6786	getContext().getTypeSize(SingleElementTy) == Size)
6787	return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6788
6789	// Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6790	if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6791	return getNaturalAlignIndirect(Ty, /ByVal=/false);
6792
6793	// Handle small structures.
6794	if (const RecordType *RT = Ty->getAs<RecordType>()) {
6795	// Structures with flexible arrays have variable length, so really
6796	// fail the size test above.
6797	const RecordDecl *RD = RT->getDecl();
6798	if (RD->hasFlexibleArrayMember())
6799	return getNaturalAlignIndirect(Ty, /ByVal=/false);
6800
6801	// The structure is passed as an unextended integer, a float, or a double.
6802	llvm::Type *PassTy;
6803	if (isFPArgumentType(SingleElementTy)) {
6804	assert(Size == 32 \|\| Size == 64);
6805	if (Size == 32)
6806	PassTy = llvm::Type::getFloatTy(getVMContext());
6807	else
6808	PassTy = llvm::Type::getDoubleTy(getVMContext());
6809	} else
6810	PassTy = llvm::IntegerType::get(getVMContext(), Size);
6811	return ABIArgInfo::getDirect(PassTy);
6812	}
6813
6814	// Non-structure compounds are passed indirectly.
6815	if (isCompoundType(Ty))
6816	return getNaturalAlignIndirect(Ty, /ByVal=/false);
6817
6818	return ABIArgInfo::getDirect(nullptr);
6819	}
6820
6821	//===----------------------------------------------------------------------===//
6822	// MSP430 ABI Implementation
6823	//===----------------------------------------------------------------------===//
6824
6825	namespace {
6826
6827	class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6828	public:
6829	MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6830	: TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6831	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
6832	CodeGen::CodeGenModule &M) const override;
6833	};
6834
6835	}
6836
6837	void MSP430TargetCodeGenInfo::setTargetAttributes(
6838	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &M) const {
6839	if (GV->isDeclaration())
6840	return;
6841	if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6842	const auto *InterruptAttr = FD->getAttr<MSP430InterruptAttr>();
6843	if (!InterruptAttr)
6844	return;
6845
6846	// Handle 'interrupt' attribute:
6847	llvm::Function *F = cast<llvm::Function>(GV);
6848
6849	// Step 1: Set ISR calling convention.
6850	F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6851
6852	// Step 2: Add attributes goodness.
6853	F->addFnAttr(llvm::Attribute::NoInline);
6854	F->addFnAttr("interrupt", llvm::utostr(InterruptAttr->getNumber()));
6855	}
6856	}
6857
6858	//===----------------------------------------------------------------------===//
6859	// MIPS ABI Implementation. This works for both little-endian and
6860	// big-endian variants.
6861	//===----------------------------------------------------------------------===//
6862
6863	namespace {
6864	class MipsABIInfo : public ABIInfo {
6865	bool IsO32;
6866	unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6867	void CoerceToIntArgs(uint64_t TySize,
6868	SmallVectorImpl<llvm::Type *> &ArgList) const;
6869	llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6870	llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6871	llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6872	public:
6873	MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6874	ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6875	StackAlignInBytes(IsO32 ? 8 : 16) {}
6876
6877	ABIArgInfo classifyReturnType(QualType RetTy) const;
6878	ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6879	void computeInfo(CGFunctionInfo &FI) const override;
6880	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6881	QualType Ty) const override;
6882	ABIArgInfo extendType(QualType Ty) const;
6883	};
6884
6885	class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6886	unsigned SizeOfUnwindException;
6887	public:
6888	MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6889	: TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6890	SizeOfUnwindException(IsO32 ? 24 : 32) {}
6891
6892	int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6893	return 29;
6894	}
6895
6896	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
6897	CodeGen::CodeGenModule &CGM) const override {
6898	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6899	if (!FD) return;
6900	llvm::Function *Fn = cast<llvm::Function>(GV);
6901
6902	if (FD->hasAttr<MipsLongCallAttr>())
6903	Fn->addFnAttr("long-call");
6904	else if (FD->hasAttr<MipsShortCallAttr>())
6905	Fn->addFnAttr("short-call");
6906
6907	// Other attributes do not have a meaning for declarations.
6908	if (GV->isDeclaration())
6909	return;
6910
6911	if (FD->hasAttr<Mips16Attr>()) {
6912	Fn->addFnAttr("mips16");
6913	}
6914	else if (FD->hasAttr<NoMips16Attr>()) {
6915	Fn->addFnAttr("nomips16");
6916	}
6917
6918	if (FD->hasAttr<MicroMipsAttr>())
6919	Fn->addFnAttr("micromips");
6920	else if (FD->hasAttr<NoMicroMipsAttr>())
6921	Fn->addFnAttr("nomicromips");
6922
6923	const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6924	if (!Attr)
6925	return;
6926
6927	const char *Kind;
6928	switch (Attr->getInterrupt()) {
6929	case MipsInterruptAttr::eic: Kind = "eic"; break;
6930	case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6931	case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6932	case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6933	case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6934	case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6935	case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6936	case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6937	case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6938	}
6939
6940	Fn->addFnAttr("interrupt", Kind);
6941
6942	}
6943
6944	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6945	llvm::Value *Address) const override;
6946
6947	unsigned getSizeOfUnwindException() const override {
6948	return SizeOfUnwindException;
6949	}
6950	};
6951	}
6952
6953	void MipsABIInfo::CoerceToIntArgs(
6954	uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6955	llvm::IntegerType *IntTy =
6956	llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6957
6958	// Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6959	for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6960	ArgList.push_back(IntTy);
6961
6962	// If necessary, add one more integer type to ArgList.
6963	unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6964
6965	if (R)
6966	ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6967	}
6968
6969	// In N32/64, an aligned double precision floating point field is passed in
6970	// a register.
6971	llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6972	SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6973
6974	if (IsO32) {
6975	CoerceToIntArgs(TySize, ArgList);
6976	return llvm::StructType::get(getVMContext(), ArgList);
6977	}
6978
6979	if (Ty->isComplexType())
6980	return CGT.ConvertType(Ty);
6981
6982	const RecordType *RT = Ty->getAs<RecordType>();
6983
6984	// Unions/vectors are passed in integer registers.
6985	if (!RT \|\| !RT->isStructureOrClassType()) {
6986	CoerceToIntArgs(TySize, ArgList);
6987	return llvm::StructType::get(getVMContext(), ArgList);
6988	}
6989
6990	const RecordDecl *RD = RT->getDecl();
6991	const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6992	(0) . __assert_fail ("!(TySize % 8) && \"Size of structure must be multiple of 8.\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 6992, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6993
6994	uint64_t LastOffset = 0;
6995	unsigned idx = 0;
6996	llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6997
6998	// Iterate over fields in the struct/class and check if there are any aligned
6999	// double fields.
7000	for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
7001	i != e; ++i, ++idx) {
7002	const QualType Ty = i->getType();
7003	const BuiltinType *BT = Ty->getAs<BuiltinType>();
7004
7005	if (!BT \|\| BT->getKind() != BuiltinType::Double)
7006	continue;
7007
7008	uint64_t Offset = Layout.getFieldOffset(idx);
7009	if (Offset % 64) // Ignore doubles that are not aligned.
7010	continue;
7011
7012	// Add ((Offset - LastOffset) / 64) args of type i64.
7013	for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
7014	ArgList.push_back(I64);
7015
7016	// Add double type.
7017	ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
7018	LastOffset = Offset + 64;
7019	}
7020
7021	CoerceToIntArgs(TySize - LastOffset, IntArgList);
7022	ArgList.append(IntArgList.begin(), IntArgList.end());
7023
7024	return llvm::StructType::get(getVMContext(), ArgList);
7025	}
7026
7027	llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
7028	uint64_t Offset) const {
7029	if (OrigOffset + MinABIStackAlignInBytes > Offset)
7030	return nullptr;
7031
7032	return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
7033	}
7034
7035	ABIArgInfo
7036	MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
7037	Ty = useFirstFieldIfTransparentUnion(Ty);
7038
7039	uint64_t OrigOffset = Offset;
7040	uint64_t TySize = getContext().getTypeSize(Ty);
7041	uint64_t Align = getContext().getTypeAlign(Ty) / 8;
7042
7043	Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
7044	(uint64_t)StackAlignInBytes);
7045	unsigned CurrOffset = llvm::alignTo(Offset, Align);
7046	Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
7047
7048	if (isAggregateTypeForABI(Ty) \|\| Ty->isVectorType()) {
7049	// Ignore empty aggregates.
7050	if (TySize == 0)
7051	return ABIArgInfo::getIgnore();
7052
7053	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
7054	Offset = OrigOffset + MinABIStackAlignInBytes;
7055	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7056	}
7057
7058	// If we have reached here, aggregates are passed directly by coercing to
7059	// another structure type. Padding is inserted if the offset of the
7060	// aggregate is unaligned.
7061	ABIArgInfo ArgInfo =
7062	ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
7063	getPaddingType(OrigOffset, CurrOffset));
7064	ArgInfo.setInReg(true);
7065	return ArgInfo;
7066	}
7067
7068	// Treat an enum type as its underlying type.
7069	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7070	Ty = EnumTy->getDecl()->getIntegerType();
7071
7072	// All integral types are promoted to the GPR width.
7073	if (Ty->isIntegralOrEnumerationType())
7074	return extendType(Ty);
7075
7076	return ABIArgInfo::getDirect(
7077	nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
7078	}
7079
7080	llvm::Type*
7081	MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
7082	const RecordType *RT = RetTy->getAs<RecordType>();
7083	SmallVector<llvm::Type*, 8> RTList;
7084
7085	if (RT && RT->isStructureOrClassType()) {
7086	const RecordDecl *RD = RT->getDecl();
7087	const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
7088	unsigned FieldCnt = Layout.getFieldCount();
7089
7090	// N32/64 returns struct/classes in floating point registers if the
7091	// following conditions are met:
7092	// 1. The size of the struct/class is no larger than 128-bit.
7093	// 2. The struct/class has one or two fields all of which are floating
7094	// point types.
7095	// 3. The offset of the first field is zero (this follows what gcc does).
7096	//
7097	// Any other composite results are returned in integer registers.
7098	//
7099	if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
7100	RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
7101	for (; b != e; ++b) {
7102	const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
7103
7104	if (!BT \|\| !BT->isFloatingPoint())
7105	break;
7106
7107	RTList.push_back(CGT.ConvertType(b->getType()));
7108	}
7109
7110	if (b == e)
7111	return llvm::StructType::get(getVMContext(), RTList,
7112	RD->hasAttr<PackedAttr>());
7113
7114	RTList.clear();
7115	}
7116	}
7117
7118	CoerceToIntArgs(Size, RTList);
7119	return llvm::StructType::get(getVMContext(), RTList);
7120	}
7121
7122	ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const {
7123	uint64_t Size = getContext().getTypeSize(RetTy);
7124
7125	if (RetTy->isVoidType())
7126	return ABIArgInfo::getIgnore();
7127
7128	// O32 doesn't treat zero-sized structs differently from other structs.
7129	// However, N32/N64 ignores zero sized return values.
7130	if (!IsO32 && Size == 0)
7131	return ABIArgInfo::getIgnore();
7132
7133	if (isAggregateTypeForABI(RetTy) \|\| RetTy->isVectorType()) {
7134	if (Size <= 128) {
7135	if (RetTy->isAnyComplexType())
7136	return ABIArgInfo::getDirect();
7137
7138	// O32 returns integer vectors in registers and N32/N64 returns all small
7139	// aggregates in registers.
7140	if (!IsO32 \|\|
7141	(RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
7142	ABIArgInfo ArgInfo =
7143	ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
7144	ArgInfo.setInReg(true);
7145	return ArgInfo;
7146	}
7147	}
7148
7149	return getNaturalAlignIndirect(RetTy);
7150	}
7151
7152	// Treat an enum type as its underlying type.
7153	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7154	RetTy = EnumTy->getDecl()->getIntegerType();
7155
7156	if (RetTy->isPromotableIntegerType())
7157	return ABIArgInfo::getExtend(RetTy);
7158
7159	if ((RetTy->isUnsignedIntegerOrEnumerationType() \|\|
7160	RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
7161	return ABIArgInfo::getSignExtend(RetTy);
7162
7163	return ABIArgInfo::getDirect();
7164	}
7165
7166	void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
7167	ABIArgInfo &RetInfo = FI.getReturnInfo();
7168	if (!getCXXABI().classifyReturnType(FI))
7169	RetInfo = classifyReturnType(FI.getReturnType());
7170
7171	// Check if a pointer to an aggregate is passed as a hidden argument.
7172	uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
7173
7174	for (auto &I : FI.arguments())
7175	I.info = classifyArgumentType(I.type, Offset);
7176	}
7177
7178	Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7179	QualType OrigTy) const {
7180	QualType Ty = OrigTy;
7181
7182	// Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
7183	// Pointers are also promoted in the same way but this only matters for N32.
7184	unsigned SlotSizeInBits = IsO32 ? 32 : 64;
7185	unsigned PtrWidth = getTarget().getPointerWidth(0);
7186	bool DidPromote = false;
7187	if ((Ty->isIntegerType() &&
7188	getContext().getIntWidth(Ty) < SlotSizeInBits) \|\|
7189	(Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
7190	DidPromote = true;
7191	Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
7192	Ty->isSignedIntegerType());
7193	}
7194
7195	auto TyInfo = getContext().getTypeInfoInChars(Ty);
7196
7197	// The alignment of things in the argument area is never larger than
7198	// StackAlignInBytes.
7199	TyInfo.second =
7200	std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
7201
7202	// MinABIStackAlignInBytes is the size of argument slots on the stack.
7203	CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
7204
7205	Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /indirect/ false,
7206	TyInfo, ArgSlotSize, /AllowHigherAlign/ true);
7207
7208
7209	// If there was a promotion, "unpromote" into a temporary.
7210	// TODO: can we just use a pointer into a subset of the original slot?
7211	if (DidPromote) {
7212	Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
7213	llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
7214
7215	// Truncate down to the right width.
7216	llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
7217	: CGF.IntPtrTy);
7218	llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
7219	if (OrigTy->isPointerType())
7220	V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
7221
7222	CGF.Builder.CreateStore(V, Temp);
7223	Addr = Temp;
7224	}
7225
7226	return Addr;
7227	}
7228
7229	ABIArgInfo MipsABIInfo::extendType(QualType Ty) const {
7230	int TySize = getContext().getTypeSize(Ty);
7231
7232	// MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
7233	if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
7234	return ABIArgInfo::getSignExtend(Ty);
7235
7236	return ABIArgInfo::getExtend(Ty);
7237	}
7238
7239	bool
7240	MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7241	llvm::Value *Address) const {
7242	// This information comes from gcc's implementation, which seems to
7243	// as canonical as it gets.
7244
7245	// Everything on MIPS is 4 bytes. Double-precision FP registers
7246	// are aliased to pairs of single-precision FP registers.
7247	llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
7248
7249	// 0-31 are the general purpose registers, $0 - $31.
7250	// 32-63 are the floating-point registers, $f0 - $f31.
7251	// 64 and 65 are the multiply/divide registers, $hi and $lo.
7252	// 66 is the (notional, I think) register for signal-handler return.
7253	AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
7254
7255	// 67-74 are the floating-point status registers, $fcc0 - $fcc7.
7256	// They are one bit wide and ignored here.
7257
7258	// 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
7259	// (coprocessor 1 is the FP unit)
7260	// 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
7261	// 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
7262	// 176-181 are the DSP accumulator registers.
7263	AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
7264	return false;
7265	}
7266
7267	//===----------------------------------------------------------------------===//
7268	// AVR ABI Implementation.
7269	//===----------------------------------------------------------------------===//
7270
7271	namespace {
7272	class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
7273	public:
7274	AVRTargetCodeGenInfo(CodeGenTypes &CGT)
7275	: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
7276
7277	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
7278	CodeGen::CodeGenModule &CGM) const override {
7279	if (GV->isDeclaration())
7280	return;
7281	const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
7282	if (!FD) return;
7283	auto *Fn = cast<llvm::Function>(GV);
7284
7285	if (FD->getAttr<AVRInterruptAttr>())
7286	Fn->addFnAttr("interrupt");
7287
7288	if (FD->getAttr<AVRSignalAttr>())
7289	Fn->addFnAttr("signal");
7290	}
7291	};
7292	}
7293
7294	//===----------------------------------------------------------------------===//
7295	// TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
7296	// Currently subclassed only to implement custom OpenCL C function attribute
7297	// handling.
7298	//===----------------------------------------------------------------------===//
7299
7300	namespace {
7301
7302	class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7303	public:
7304	TCETargetCodeGenInfo(CodeGenTypes &CGT)
7305	: DefaultTargetCodeGenInfo(CGT) {}
7306
7307	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
7308	CodeGen::CodeGenModule &M) const override;
7309	};
7310
7311	void TCETargetCodeGenInfo::setTargetAttributes(
7312	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &M) const {
7313	if (GV->isDeclaration())
7314	return;
7315	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7316	if (!FD) return;
7317
7318	llvm::Function *F = cast<llvm::Function>(GV);
7319
7320	if (M.getLangOpts().OpenCL) {
7321	if (FD->hasAttr<OpenCLKernelAttr>()) {
7322	// OpenCL C Kernel functions are not subject to inlining
7323	F->addFnAttr(llvm::Attribute::NoInline);
7324	const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7325	if (Attr) {
7326	// Convert the reqd_work_group_size() attributes to metadata.
7327	llvm::LLVMContext &Context = F->getContext();
7328	llvm::NamedMDNode *OpenCLMetadata =
7329	M.getModule().getOrInsertNamedMetadata(
7330	"opencl.kernel_wg_size_info");
7331
7332	SmallVector<llvm::Metadata *, 5> Operands;
7333	Operands.push_back(llvm::ConstantAsMetadata::get(F));
7334
7335	Operands.push_back(
7336	llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7337	M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7338	Operands.push_back(
7339	llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7340	M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7341	Operands.push_back(
7342	llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7343	M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7344
7345	// Add a boolean constant operand for "required" (true) or "hint"
7346	// (false) for implementing the work_group_size_hint attr later.
7347	// Currently always true as the hint is not yet implemented.
7348	Operands.push_back(
7349	llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7350	OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7351	}
7352	}
7353	}
7354	}
7355
7356	}
7357
7358	//===----------------------------------------------------------------------===//
7359	// Hexagon ABI Implementation
7360	//===----------------------------------------------------------------------===//
7361
7362	namespace {
7363
7364	class HexagonABIInfo : public ABIInfo {
7365
7366
7367	public:
7368	HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7369
7370	private:
7371
7372	ABIArgInfo classifyReturnType(QualType RetTy) const;
7373	ABIArgInfo classifyArgumentType(QualType RetTy) const;
7374
7375	void computeInfo(CGFunctionInfo &FI) const override;
7376
7377	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7378	QualType Ty) const override;
7379	};
7380
7381	class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7382	public:
7383	HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7384	:TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7385
7386	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7387	return 29;
7388	}
7389	};
7390
7391	}
7392
7393	void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7394	if (!getCXXABI().classifyReturnType(FI))
7395	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7396	for (auto &I : FI.arguments())
7397	I.info = classifyArgumentType(I.type);
7398	}
7399
7400	ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const {
7401	if (!isAggregateTypeForABI(Ty)) {
7402	// Treat an enum type as its underlying type.
7403	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7404	Ty = EnumTy->getDecl()->getIntegerType();
7405
7406	return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
7407	: ABIArgInfo::getDirect());
7408	}
7409
7410	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7411	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7412
7413	// Ignore empty records.
7414	if (isEmptyRecord(getContext(), Ty, true))
7415	return ABIArgInfo::getIgnore();
7416
7417	uint64_t Size = getContext().getTypeSize(Ty);
7418	if (Size > 64)
7419	return getNaturalAlignIndirect(Ty, /ByVal=/true);
7420	// Pass in the smallest viable integer type.
7421	else if (Size > 32)
7422	return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7423	else if (Size > 16)
7424	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7425	else if (Size > 8)
7426	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7427	else
7428	return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7429	}
7430
7431	ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const {
7432	if (RetTy->isVoidType())
7433	return ABIArgInfo::getIgnore();
7434
7435	// Large vector types should be returned via memory.
7436	if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7437	return getNaturalAlignIndirect(RetTy);
7438
7439	if (!isAggregateTypeForABI(RetTy)) {
7440	// Treat an enum type as its underlying type.
7441	if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7442	RetTy = EnumTy->getDecl()->getIntegerType();
7443
7444	return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
7445	: ABIArgInfo::getDirect());
7446	}
7447
7448	if (isEmptyRecord(getContext(), RetTy, true))
7449	return ABIArgInfo::getIgnore();
7450
7451	// Aggregates <= 8 bytes are returned in r0; other aggregates
7452	// are returned indirectly.
7453	uint64_t Size = getContext().getTypeSize(RetTy);
7454	if (Size <= 64) {
7455	// Return in the smallest viable integer type.
7456	if (Size <= 8)
7457	return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7458	if (Size <= 16)
7459	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7460	if (Size <= 32)
7461	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7462	return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7463	}
7464
7465	return getNaturalAlignIndirect(RetTy, /ByVal=/true);
7466	}
7467
7468	Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7469	QualType Ty) const {
7470	// FIXME: Someone needs to audit that this handle alignment correctly.
7471	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /indirect/ false,
7472	getContext().getTypeInfoInChars(Ty),
7473	CharUnits::fromQuantity(4),
7474	/AllowHigherAlign/ true);
7475	}
7476
7477	//===----------------------------------------------------------------------===//
7478	// Lanai ABI Implementation
7479	//===----------------------------------------------------------------------===//
7480
7481	namespace {
7482	class LanaiABIInfo : public DefaultABIInfo {
7483	public:
7484	LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7485
7486	bool shouldUseInReg(QualType Ty, CCState &State) const;
7487
7488	void computeInfo(CGFunctionInfo &FI) const override {
7489	CCState State(FI.getCallingConvention());
7490	// Lanai uses 4 registers to pass arguments unless the function has the
7491	// regparm attribute set.
7492	if (FI.getHasRegParm()) {
7493	State.FreeRegs = FI.getRegParm();
7494	} else {
7495	State.FreeRegs = 4;
7496	}
7497
7498	if (!getCXXABI().classifyReturnType(FI))
7499	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7500	for (auto &I : FI.arguments())
7501	I.info = classifyArgumentType(I.type, State);
7502	}
7503
7504	ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7505	ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7506	};
7507	} // end anonymous namespace
7508
7509	bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7510	unsigned Size = getContext().getTypeSize(Ty);
7511	unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7512
7513	if (SizeInRegs == 0)
7514	return false;
7515
7516	if (SizeInRegs > State.FreeRegs) {
7517	State.FreeRegs = 0;
7518	return false;
7519	}
7520
7521	State.FreeRegs -= SizeInRegs;
7522
7523	return true;
7524	}
7525
7526	ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7527	CCState &State) const {
7528	if (!ByVal) {
7529	if (State.FreeRegs) {
7530	--State.FreeRegs; // Non-byval indirects just use one pointer.
7531	return getNaturalAlignIndirectInReg(Ty);
7532	}
7533	return getNaturalAlignIndirect(Ty, false);
7534	}
7535
7536	// Compute the byval alignment.
7537	const unsigned MinABIStackAlignInBytes = 4;
7538	unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7539	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /ByVal=/true,
7540	/Realign=/TypeAlign >
7541	MinABIStackAlignInBytes);
7542	}
7543
7544	ABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty,
7545	CCState &State) const {
7546	// Check with the C++ ABI first.
7547	const RecordType *RT = Ty->getAs<RecordType>();
7548	if (RT) {
7549	CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
7550	if (RAA == CGCXXABI::RAA_Indirect) {
7551	return getIndirectResult(Ty, /ByVal=/false, State);
7552	} else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7553	return getNaturalAlignIndirect(Ty, /ByRef=/true);
7554	}
7555	}
7556
7557	if (isAggregateTypeForABI(Ty)) {
7558	// Structures with flexible arrays are always indirect.
7559	if (RT && RT->getDecl()->hasFlexibleArrayMember())
7560	return getIndirectResult(Ty, /ByVal=/true, State);
7561
7562	// Ignore empty structs/unions.
7563	if (isEmptyRecord(getContext(), Ty, true))
7564	return ABIArgInfo::getIgnore();
7565
7566	llvm::LLVMContext &LLVMContext = getVMContext();
7567	unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7568	if (SizeInRegs <= State.FreeRegs) {
7569	llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7570	SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7571	llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7572	State.FreeRegs -= SizeInRegs;
7573	return ABIArgInfo::getDirectInReg(Result);
7574	} else {
7575	State.FreeRegs = 0;
7576	}
7577	return getIndirectResult(Ty, true, State);
7578	}
7579
7580	// Treat an enum type as its underlying type.
7581	if (const auto *EnumTy = Ty->getAs<EnumType>())
7582	Ty = EnumTy->getDecl()->getIntegerType();
7583
7584	bool InReg = shouldUseInReg(Ty, State);
7585	if (Ty->isPromotableIntegerType()) {
7586	if (InReg)
7587	return ABIArgInfo::getDirectInReg();
7588	return ABIArgInfo::getExtend(Ty);
7589	}
7590	if (InReg)
7591	return ABIArgInfo::getDirectInReg();
7592	return ABIArgInfo::getDirect();
7593	}
7594
7595	namespace {
7596	class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7597	public:
7598	LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7599	: TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7600	};
7601	}
7602
7603	//===----------------------------------------------------------------------===//
7604	// AMDGPU ABI Implementation
7605	//===----------------------------------------------------------------------===//
7606
7607	namespace {
7608
7609	class AMDGPUABIInfo final : public DefaultABIInfo {
7610	private:
7611	static const unsigned MaxNumRegsForArgsRet = 16;
7612
7613	unsigned numRegsForType(QualType Ty) const;
7614
7615	bool isHomogeneousAggregateBaseType(QualType Ty) const override;
7616	bool isHomogeneousAggregateSmallEnough(const Type *Base,
7617	uint64_t Members) const override;
7618
7619	public:
7620	explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
7621	DefaultABIInfo(CGT) {}
7622
7623	ABIArgInfo classifyReturnType(QualType RetTy) const;
7624	ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
7625	ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const;
7626
7627	void computeInfo(CGFunctionInfo &FI) const override;
7628	};
7629
7630	bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
7631	return true;
7632	}
7633
7634	bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
7635	const Type *Base, uint64_t Members) const {
7636	uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32;
7637
7638	// Homogeneous Aggregates may occupy at most 16 registers.
7639	return Members * NumRegs <= MaxNumRegsForArgsRet;
7640	}
7641
7642	/// Estimate number of registers the type will use when passed in registers.
7643	unsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const {
7644	unsigned NumRegs = 0;
7645
7646	if (const VectorType *VT = Ty->getAs<VectorType>()) {
7647	// Compute from the number of elements. The reported size is based on the
7648	// in-memory size, which includes the padding 4th element for 3-vectors.
7649	QualType EltTy = VT->getElementType();
7650	unsigned EltSize = getContext().getTypeSize(EltTy);
7651
7652	// 16-bit element vectors should be passed as packed.
7653	if (EltSize == 16)
7654	return (VT->getNumElements() + 1) / 2;
7655
7656	unsigned EltNumRegs = (EltSize + 31) / 32;
7657	return EltNumRegs * VT->getNumElements();
7658	}
7659
7660	if (const RecordType *RT = Ty->getAs<RecordType>()) {
7661	const RecordDecl *RD = RT->getDecl();
7662	hasFlexibleArrayMember()", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7662, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!RD->hasFlexibleArrayMember());
7663
7664	for (const FieldDecl *Field : RD->fields()) {
7665	QualType FieldTy = Field->getType();
7666	NumRegs += numRegsForType(FieldTy);
7667	}
7668
7669	return NumRegs;
7670	}
7671
7672	return (getContext().getTypeSize(Ty) + 31) / 32;
7673	}
7674
7675	void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7676	llvm::CallingConv::ID CC = FI.getCallingConvention();
7677
7678	if (!getCXXABI().classifyReturnType(FI))
7679	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
7680
7681	unsigned NumRegsLeft = MaxNumRegsForArgsRet;
7682	for (auto &Arg : FI.arguments()) {
7683	if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
7684	Arg.info = classifyKernelArgumentType(Arg.type);
7685	} else {
7686	Arg.info = classifyArgumentType(Arg.type, NumRegsLeft);
7687	}
7688	}
7689	}
7690
7691	ABIArgInfo AMDGPUABIInfo::classifyReturnType(QualType RetTy) const {
7692	if (isAggregateTypeForABI(RetTy)) {
7693	// Records with non-trivial destructors/copy-constructors should not be
7694	// returned by value.
7695	if (!getRecordArgABI(RetTy, getCXXABI())) {
7696	// Ignore empty structs/unions.
7697	if (isEmptyRecord(getContext(), RetTy, true))
7698	return ABIArgInfo::getIgnore();
7699
7700	// Lower single-element structs to just return a regular value.
7701	if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
7702	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7703
7704	if (const RecordType *RT = RetTy->getAs<RecordType>()) {
7705	const RecordDecl *RD = RT->getDecl();
7706	if (RD->hasFlexibleArrayMember())
7707	return DefaultABIInfo::classifyReturnType(RetTy);
7708	}
7709
7710	// Pack aggregates <= 4 bytes into single VGPR or pair.
7711	uint64_t Size = getContext().getTypeSize(RetTy);
7712	if (Size <= 16)
7713	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7714
7715	if (Size <= 32)
7716	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7717
7718	if (Size <= 64) {
7719	llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7720	return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7721	}
7722
7723	if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet)
7724	return ABIArgInfo::getDirect();
7725	}
7726	}
7727
7728	// Otherwise just do the default thing.
7729	return DefaultABIInfo::classifyReturnType(RetTy);
7730	}
7731
7732	/// For kernels all parameters are really passed in a special buffer. It doesn't
7733	/// make sense to pass anything byval, so everything must be direct.
7734	ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
7735	Ty = useFirstFieldIfTransparentUnion(Ty);
7736
7737	// TODO: Can we omit empty structs?
7738
7739	// Coerce single element structs to its element.
7740	if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7741	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7742
7743	// If we set CanBeFlattened to true, CodeGen will expand the struct to its
7744	// individual elements, which confuses the Clover OpenCL backend; therefore we
7745	// have to set it to false here. Other args of getDirect() are just defaults.
7746	return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7747	}
7748
7749	ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
7750	unsigned &NumRegsLeft) const {
7751	(0) . __assert_fail ("NumRegsLeft <= MaxNumRegsForArgsRet && \"register estimate underflow\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7751, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
7752
7753	Ty = useFirstFieldIfTransparentUnion(Ty);
7754
7755	if (isAggregateTypeForABI(Ty)) {
7756	// Records with non-trivial destructors/copy-constructors should not be
7757	// passed by value.
7758	if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
7759	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7760
7761	// Ignore empty structs/unions.
7762	if (isEmptyRecord(getContext(), Ty, true))
7763	return ABIArgInfo::getIgnore();
7764
7765	// Lower single-element structs to just pass a regular value. TODO: We
7766	// could do reasonable-size multiple-element structs too, using getExpand(),
7767	// though watch out for things like bitfields.
7768	if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7769	return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7770
7771	if (const RecordType *RT = Ty->getAs<RecordType>()) {
7772	const RecordDecl *RD = RT->getDecl();
7773	if (RD->hasFlexibleArrayMember())
7774	return DefaultABIInfo::classifyArgumentType(Ty);
7775	}
7776
7777	// Pack aggregates <= 8 bytes into single VGPR or pair.
7778	uint64_t Size = getContext().getTypeSize(Ty);
7779	if (Size <= 64) {
7780	unsigned NumRegs = (Size + 31) / 32;
7781	NumRegsLeft -= std::min(NumRegsLeft, NumRegs);
7782
7783	if (Size <= 16)
7784	return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7785
7786	if (Size <= 32)
7787	return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7788
7789	// XXX: Should this be i64 instead, and should the limit increase?
7790	llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7791	return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7792	}
7793
7794	if (NumRegsLeft > 0) {
7795	unsigned NumRegs = numRegsForType(Ty);
7796	if (NumRegsLeft >= NumRegs) {
7797	NumRegsLeft -= NumRegs;
7798	return ABIArgInfo::getDirect();
7799	}
7800	}
7801	}
7802
7803	// Otherwise just do the default thing.
7804	ABIArgInfo ArgInfo = DefaultABIInfo::classifyArgumentType(Ty);
7805	if (!ArgInfo.isIndirect()) {
7806	unsigned NumRegs = numRegsForType(Ty);
7807	NumRegsLeft -= std::min(NumRegs, NumRegsLeft);
7808	}
7809
7810	return ArgInfo;
7811	}
7812
7813	class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7814	public:
7815	AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7816	: TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7817	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
7818	CodeGen::CodeGenModule &M) const override;
7819	unsigned getOpenCLKernelCallingConv() const override;
7820
7821	llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7822	llvm::PointerType *T, QualType QT) const override;
7823
7824	LangAS getASTAllocaAddressSpace() const override {
7825	return getLangASFromTargetAS(
7826	getABIInfo().getDataLayout().getAllocaAddrSpace());
7827	}
7828	LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
7829	const VarDecl *D) const override;
7830	llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts,
7831	SyncScope Scope,
7832	llvm::AtomicOrdering Ordering,
7833	llvm::LLVMContext &Ctx) const override;
7834	llvm::Function *
7835	createEnqueuedBlockKernel(CodeGenFunction &CGF,
7836	llvm::Function *BlockInvokeFunc,
7837	llvm::Value *BlockLiteral) const override;
7838	bool shouldEmitStaticExternCAliases() const override;
7839	void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
7840	};
7841	}
7842
7843	static bool requiresAMDGPUProtectedVisibility(const Decl *D,
7844	llvm::GlobalValue *GV) {
7845	if (GV->getVisibility() != llvm::GlobalValue::HiddenVisibility)
7846	return false;
7847
7848	return D->hasAttr<OpenCLKernelAttr>() \|\|
7849	(isa<FunctionDecl>(D) && D->hasAttr<CUDAGlobalAttr>()) \|\|
7850	(isa<VarDecl>(D) && D->hasAttr<CUDADeviceAttr>());
7851	}
7852
7853	void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7854	const Decl D, llvm::GlobalValue GV, CodeGen::CodeGenModule &M) const {
7855	if (requiresAMDGPUProtectedVisibility(D, GV)) {
7856	GV->setVisibility(llvm::GlobalValue::ProtectedVisibility);
7857	GV->setDSOLocal(true);
7858	}
7859
7860	if (GV->isDeclaration())
7861	return;
7862	const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7863	if (!FD)
7864	return;
7865
7866	llvm::Function *F = cast<llvm::Function>(GV);
7867
7868	const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7869	FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7870
7871	if (M.getLangOpts().OpenCL && FD->hasAttr<OpenCLKernelAttr>() &&
7872	(M.getTriple().getOS() == llvm::Triple::AMDHSA))
7873	F->addFnAttr("amdgpu-implicitarg-num-bytes", "48");
7874
7875	const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7876	if (ReqdWGS \|\| FlatWGS) {
7877	unsigned Min = 0;
7878	unsigned Max = 0;
7879	if (FlatWGS) {
7880	Min = FlatWGS->getMin()
7881	->EvaluateKnownConstInt(M.getContext())
7882	.getExtValue();
7883	Max = FlatWGS->getMax()
7884	->EvaluateKnownConstInt(M.getContext())
7885	.getExtValue();
7886	}
7887	if (ReqdWGS && Min == 0 && Max == 0)
7888	Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7889
7890	if (Min != 0) {
7891	(0) . __assert_fail ("Min <= Max && \"Min must be less than or equal Max\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7891, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Min <= Max && "Min must be less than or equal Max");
7892
7893	std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7894	F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7895	} else
7896	(0) . __assert_fail ("Max == 0 && \"Max must be zero\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7896, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Max == 0 && "Max must be zero");
7897	}
7898
7899	if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7900	unsigned Min =
7901	Attr->getMin()->EvaluateKnownConstInt(M.getContext()).getExtValue();
7902	unsigned Max = Attr->getMax() ? Attr->getMax()
7903	->EvaluateKnownConstInt(M.getContext())
7904	.getExtValue()
7905	: 0;
7906
7907	if (Min != 0) {
7908	(0) . __assert_fail ("(Max == 0 \|\| Min <= Max) && \"Min must be less than or equal Max\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7908, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert((Max == 0 \|\| Min <= Max) && "Min must be less than or equal Max");
7909
7910	std::string AttrVal = llvm::utostr(Min);
7911	if (Max != 0)
7912	AttrVal = AttrVal + "," + llvm::utostr(Max);
7913	F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7914	} else
7915	(0) . __assert_fail ("Max == 0 && \"Max must be zero\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7915, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Max == 0 && "Max must be zero");
7916	}
7917
7918	if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7919	unsigned NumSGPR = Attr->getNumSGPR();
7920
7921	if (NumSGPR != 0)
7922	F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7923	}
7924
7925	if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7926	uint32_t NumVGPR = Attr->getNumVGPR();
7927
7928	if (NumVGPR != 0)
7929	F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7930	}
7931	}
7932
7933	unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7934	return llvm::CallingConv::AMDGPU_KERNEL;
7935	}
7936
7937	// Currently LLVM assumes null pointers always have value 0,
7938	// which results in incorrectly transformed IR. Therefore, instead of
7939	// emitting null pointers in private and local address spaces, a null
7940	// pointer in generic address space is emitted which is casted to a
7941	// pointer in local or private address space.
7942	llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7943	const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7944	QualType QT) const {
7945	if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7946	return llvm::ConstantPointerNull::get(PT);
7947
7948	auto &Ctx = CGM.getContext();
7949	auto NPT = llvm::PointerType::get(PT->getElementType(),
7950	Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7951	return llvm::ConstantExpr::getAddrSpaceCast(
7952	llvm::ConstantPointerNull::get(NPT), PT);
7953	}
7954
7955	LangAS
7956	AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7957	const VarDecl *D) const {
7958	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7960, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!CGM.getLangOpts().OpenCL &&
7959	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7960, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7960	(0) . __assert_fail ("!CGM.getLangOpts().OpenCL && !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && \"Address space agnostic languages only\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 7960, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Address space agnostic languages only");
7961	LangAS DefaultGlobalAS = getLangASFromTargetAS(
7962	CGM.getContext().getTargetAddressSpace(LangAS::opencl_global));
7963	if (!D)
7964	return DefaultGlobalAS;
7965
7966	LangAS AddrSpace = D->getType().getAddressSpace();
7967	assert(AddrSpace == LangAS::Default \|\| isTargetAddressSpace(AddrSpace));
7968	if (AddrSpace != LangAS::Default)
7969	return AddrSpace;
7970
7971	if (CGM.isTypeConstant(D->getType(), false)) {
7972	if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7973	return ConstAS.getValue();
7974	}
7975	return DefaultGlobalAS;
7976	}
7977
7978	llvm::SyncScope::ID
7979	AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
7980	SyncScope Scope,
7981	llvm::AtomicOrdering Ordering,
7982	llvm::LLVMContext &Ctx) const {
7983	std::string Name;
7984	switch (Scope) {
7985	case SyncScope::OpenCLWorkGroup:
7986	Name = "workgroup";
7987	break;
7988	case SyncScope::OpenCLDevice:
7989	Name = "agent";
7990	break;
7991	case SyncScope::OpenCLAllSVMDevices:
7992	Name = "";
7993	break;
7994	case SyncScope::OpenCLSubGroup:
7995	Name = "wavefront";
7996	}
7997
7998	if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
7999	if (!Name.empty())
8000	Name = Twine(Twine(Name) + Twine("-")).str();
8001
8002	Name = Twine(Twine(Name) + Twine("one-as")).str();
8003	}
8004
8005	return Ctx.getOrInsertSyncScopeID(Name);
8006	}
8007
8008	bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
8009	return false;
8010	}
8011
8012	void AMDGPUTargetCodeGenInfo::setCUDAKernelCallingConvention(
8013	const FunctionType *&FT) const {
8014	FT = getABIInfo().getContext().adjustFunctionType(
8015	FT, FT->getExtInfo().withCallingConv(CC_OpenCLKernel));
8016	}
8017
8018	//===----------------------------------------------------------------------===//
8019	// SPARC v8 ABI Implementation.
8020	// Based on the SPARC Compliance Definition version 2.4.1.
8021	//
8022	// Ensures that complex values are passed in registers.
8023	//
8024	namespace {
8025	class SparcV8ABIInfo : public DefaultABIInfo {
8026	public:
8027	SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8028
8029	private:
8030	ABIArgInfo classifyReturnType(QualType RetTy) const;
8031	void computeInfo(CGFunctionInfo &FI) const override;
8032	};
8033	} // end anonymous namespace
8034
8035
8036	ABIArgInfo
8037	SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
8038	if (Ty->isAnyComplexType()) {
8039	return ABIArgInfo::getDirect();
8040	}
8041	else {
8042	return DefaultABIInfo::classifyReturnType(Ty);
8043	}
8044	}
8045
8046	void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8047
8048	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
8049	for (auto &Arg : FI.arguments())
8050	Arg.info = classifyArgumentType(Arg.type);
8051	}
8052
8053	namespace {
8054	class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
8055	public:
8056	SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
8057	: TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
8058	};
8059	} // end anonymous namespace
8060
8061	//===----------------------------------------------------------------------===//
8062	// SPARC v9 ABI Implementation.
8063	// Based on the SPARC Compliance Definition version 2.4.1.
8064	//
8065	// Function arguments a mapped to a nominal "parameter array" and promoted to
8066	// registers depending on their type. Each argument occupies 8 or 16 bytes in
8067	// the array, structs larger than 16 bytes are passed indirectly.
8068	//
8069	// One case requires special care:
8070	//
8071	// struct mixed {
8072	// int i;
8073	// float f;
8074	// };
8075	//
8076	// When a struct mixed is passed by value, it only occupies 8 bytes in the
8077	// parameter array, but the int is passed in an integer register, and the float
8078	// is passed in a floating point register. This is represented as two arguments
8079	// with the LLVM IR inreg attribute:
8080	//
8081	// declare void f(i32 inreg %i, float inreg %f)
8082	//
8083	// The code generator will only allocate 4 bytes from the parameter array for
8084	// the inreg arguments. All other arguments are allocated a multiple of 8
8085	// bytes.
8086	//
8087	namespace {
8088	class SparcV9ABIInfo : public ABIInfo {
8089	public:
8090	SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
8091
8092	private:
8093	ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
8094	void computeInfo(CGFunctionInfo &FI) const override;
8095	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8096	QualType Ty) const override;
8097
8098	// Coercion type builder for structs passed in registers. The coercion type
8099	// serves two purposes:
8100	//
8101	// 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
8102	// in registers.
8103	// 2. Expose aligned floating point elements as first-level elements, so the
8104	// code generator knows to pass them in floating point registers.
8105	//
8106	// We also compute the InReg flag which indicates that the struct contains
8107	// aligned 32-bit floats.
8108	//
8109	struct CoerceBuilder {
8110	llvm::LLVMContext &Context;
8111	const llvm::DataLayout &DL;
8112	SmallVector<llvm::Type*, 8> Elems;
8113	uint64_t Size;
8114	bool InReg;
8115
8116	CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
8117	: Context(c), DL(dl), Size(0), InReg(false) {}
8118
8119	// Pad Elems with integers until Size is ToSize.
8120	void pad(uint64_t ToSize) {
8121	(0) . __assert_fail ("ToSize >= Size && \"Cannot remove elements\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8121, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(ToSize >= Size && "Cannot remove elements");
8122	if (ToSize == Size)
8123	return;
8124
8125	// Finish the current 64-bit word.
8126	uint64_t Aligned = llvm::alignTo(Size, 64);
8127	if (Aligned > Size && Aligned <= ToSize) {
8128	Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
8129	Size = Aligned;
8130	}
8131
8132	// Add whole 64-bit words.
8133	while (Size + 64 <= ToSize) {
8134	Elems.push_back(llvm::Type::getInt64Ty(Context));
8135	Size += 64;
8136	}
8137
8138	// Final in-word padding.
8139	if (Size < ToSize) {
8140	Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
8141	Size = ToSize;
8142	}
8143	}
8144
8145	// Add a floating point element at Offset.
8146	void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
8147	// Unaligned floats are treated as integers.
8148	if (Offset % Bits)
8149	return;
8150	// The InReg flag is only required if there are any floats < 64 bits.
8151	if (Bits < 64)
8152	InReg = true;
8153	pad(Offset);
8154	Elems.push_back(Ty);
8155	Size = Offset + Bits;
8156	}
8157
8158	// Add a struct type to the coercion type, starting at Offset (in bits).
8159	void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
8160	const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
8161	for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
8162	llvm::Type *ElemTy = StrTy->getElementType(i);
8163	uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
8164	switch (ElemTy->getTypeID()) {
8165	case llvm::Type::StructTyID:
8166	addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
8167	break;
8168	case llvm::Type::FloatTyID:
8169	addFloat(ElemOffset, ElemTy, 32);
8170	break;
8171	case llvm::Type::DoubleTyID:
8172	addFloat(ElemOffset, ElemTy, 64);
8173	break;
8174	case llvm::Type::FP128TyID:
8175	addFloat(ElemOffset, ElemTy, 128);
8176	break;
8177	case llvm::Type::PointerTyID:
8178	if (ElemOffset % 64 == 0) {
8179	pad(ElemOffset);
8180	Elems.push_back(ElemTy);
8181	Size += 64;
8182	}
8183	break;
8184	default:
8185	break;
8186	}
8187	}
8188	}
8189
8190	// Check if Ty is a usable substitute for the coercion type.
8191	bool isUsableType(llvm::StructType *Ty) const {
8192	return llvm::makeArrayRef(Elems) == Ty->elements();
8193	}
8194
8195	// Get the coercion type as a literal struct type.
8196	llvm::Type *getType() const {
8197	if (Elems.size() == 1)
8198	return Elems.front();
8199	else
8200	return llvm::StructType::get(Context, Elems);
8201	}
8202	};
8203	};
8204	} // end anonymous namespace
8205
8206	ABIArgInfo
8207	SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
8208	if (Ty->isVoidType())
8209	return ABIArgInfo::getIgnore();
8210
8211	uint64_t Size = getContext().getTypeSize(Ty);
8212
8213	// Anything too big to fit in registers is passed with an explicit indirect
8214	// pointer / sret pointer.
8215	if (Size > SizeLimit)
8216	return getNaturalAlignIndirect(Ty, /ByVal=/false);
8217
8218	// Treat an enum type as its underlying type.
8219	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8220	Ty = EnumTy->getDecl()->getIntegerType();
8221
8222	// Integer types smaller than a register are extended.
8223	if (Size < 64 && Ty->isIntegerType())
8224	return ABIArgInfo::getExtend(Ty);
8225
8226	// Other non-aggregates go in registers.
8227	if (!isAggregateTypeForABI(Ty))
8228	return ABIArgInfo::getDirect();
8229
8230	// If a C++ object has either a non-trivial copy constructor or a non-trivial
8231	// destructor, it is passed with an explicit indirect pointer / sret pointer.
8232	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
8233	return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
8234
8235	// This is a small aggregate type that should be passed in registers.
8236	// Build a coercion type from the LLVM struct type.
8237	llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
8238	if (!StrTy)
8239	return ABIArgInfo::getDirect();
8240
8241	CoerceBuilder CB(getVMContext(), getDataLayout());
8242	CB.addStruct(0, StrTy);
8243	CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
8244
8245	// Try to use the original type for coercion.
8246	llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
8247
8248	if (CB.InReg)
8249	return ABIArgInfo::getDirectInReg(CoerceTy);
8250	else
8251	return ABIArgInfo::getDirect(CoerceTy);
8252	}
8253
8254	Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8255	QualType Ty) const {
8256	ABIArgInfo AI = classifyType(Ty, 16 * 8);
8257	llvm::Type *ArgTy = CGT.ConvertType(Ty);
8258	if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8259	AI.setCoerceToType(ArgTy);
8260
8261	CharUnits SlotSize = CharUnits::fromQuantity(8);
8262
8263	CGBuilderTy &Builder = CGF.Builder;
8264	Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
8265	llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8266
8267	auto TypeInfo = getContext().getTypeInfoInChars(Ty);
8268
8269	Address ArgAddr = Address::invalid();
8270	CharUnits Stride;
8271	switch (AI.getKind()) {
8272	case ABIArgInfo::Expand:
8273	case ABIArgInfo::CoerceAndExpand:
8274	case ABIArgInfo::InAlloca:
8275	llvm_unreachable("Unsupported ABI kind for va_arg");
8276
8277	case ABIArgInfo::Extend: {
8278	Stride = SlotSize;
8279	CharUnits Offset = SlotSize - TypeInfo.first;
8280	ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
8281	break;
8282	}
8283
8284	case ABIArgInfo::Direct: {
8285	auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
8286	Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
8287	ArgAddr = Addr;
8288	break;
8289	}
8290
8291	case ABIArgInfo::Indirect:
8292	Stride = SlotSize;
8293	ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
8294	ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
8295	TypeInfo.second);
8296	break;
8297
8298	case ABIArgInfo::Ignore:
8299	return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
8300	}
8301
8302	// Update VAList.
8303	Address NextPtr = Builder.CreateConstInBoundsByteGEP(Addr, Stride, "ap.next");
8304	Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
8305
8306	return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
8307	}
8308
8309	void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8310	FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
8311	for (auto &I : FI.arguments())
8312	I.info = classifyType(I.type, 16 * 8);
8313	}
8314
8315	namespace {
8316	class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
8317	public:
8318	SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
8319	: TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
8320
8321	int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
8322	return 14;
8323	}
8324
8325	bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8326	llvm::Value *Address) const override;
8327	};
8328	} // end anonymous namespace
8329
8330	bool
8331	SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8332	llvm::Value *Address) const {
8333	// This is calculated from the LLVM and GCC tables and verified
8334	// against gcc output. AFAIK all ABIs use the same encoding.
8335
8336	CodeGen::CGBuilderTy &Builder = CGF.Builder;
8337
8338	llvm::IntegerType *i8 = CGF.Int8Ty;
8339	llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
8340	llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
8341
8342	// 0-31: the 8-byte general-purpose registers
8343	AssignToArrayRange(Builder, Address, Eight8, 0, 31);
8344
8345	// 32-63: f0-31, the 4-byte floating-point registers
8346	AssignToArrayRange(Builder, Address, Four8, 32, 63);
8347
8348	// Y = 64
8349	// PSR = 65
8350	// WIM = 66
8351	// TBR = 67
8352	// PC = 68
8353	// NPC = 69
8354	// FSR = 70
8355	// CSR = 71
8356	AssignToArrayRange(Builder, Address, Eight8, 64, 71);
8357
8358	// 72-87: d0-15, the 8-byte floating-point registers
8359	AssignToArrayRange(Builder, Address, Eight8, 72, 87);
8360
8361	return false;
8362	}
8363
8364	// ARC ABI implementation.
8365	namespace {
8366
8367	class ARCABIInfo : public DefaultABIInfo {
8368	public:
8369	using DefaultABIInfo::DefaultABIInfo;
8370
8371	private:
8372	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8373	QualType Ty) const override;
8374
8375	void updateState(const ABIArgInfo &Info, QualType Ty, CCState &State) const {
8376	if (!State.FreeRegs)
8377	return;
8378	if (Info.isIndirect() && Info.getInReg())
8379	State.FreeRegs--;
8380	else if (Info.isDirect() && Info.getInReg()) {
8381	unsigned sz = (getContext().getTypeSize(Ty) + 31) / 32;
8382	if (sz < State.FreeRegs)
8383	State.FreeRegs -= sz;
8384	else
8385	State.FreeRegs = 0;
8386	}
8387	}
8388
8389	void computeInfo(CGFunctionInfo &FI) const override {
8390	CCState State(FI.getCallingConvention());
8391	// ARC uses 8 registers to pass arguments.
8392	State.FreeRegs = 8;
8393
8394	if (!getCXXABI().classifyReturnType(FI))
8395	FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
8396	updateState(FI.getReturnInfo(), FI.getReturnType(), State);
8397	for (auto &I : FI.arguments()) {
8398	I.info = classifyArgumentType(I.type, State.FreeRegs);
8399	updateState(I.info, I.type, State);
8400	}
8401	}
8402
8403	ABIArgInfo getIndirectByRef(QualType Ty, bool HasFreeRegs) const;
8404	ABIArgInfo getIndirectByValue(QualType Ty) const;
8405	ABIArgInfo classifyArgumentType(QualType Ty, uint8_t FreeRegs) const;
8406	ABIArgInfo classifyReturnType(QualType RetTy) const;
8407	};
8408
8409	class ARCTargetCodeGenInfo : public TargetCodeGenInfo {
8410	public:
8411	ARCTargetCodeGenInfo(CodeGenTypes &CGT)
8412	: TargetCodeGenInfo(new ARCABIInfo(CGT)) {}
8413	};
8414
8415
8416	ABIArgInfo ARCABIInfo::getIndirectByRef(QualType Ty, bool HasFreeRegs) const {
8417	return HasFreeRegs ? getNaturalAlignIndirectInReg(Ty) :
8418	getNaturalAlignIndirect(Ty, false);
8419	}
8420
8421	ABIArgInfo ARCABIInfo::getIndirectByValue(QualType Ty) const {
8422	// Compute the byval alignment.
8423	const unsigned MinABIStackAlignInBytes = 4;
8424	unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
8425	return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /ByVal=/true,
8426	TypeAlign > MinABIStackAlignInBytes);
8427	}
8428
8429	Address ARCABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8430	QualType Ty) const {
8431	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /indirect/ false,
8432	getContext().getTypeInfoInChars(Ty),
8433	CharUnits::fromQuantity(4), true);
8434	}
8435
8436	ABIArgInfo ARCABIInfo::classifyArgumentType(QualType Ty,
8437	uint8_t FreeRegs) const {
8438	// Handle the generic C++ ABI.
8439	const RecordType *RT = Ty->getAs<RecordType>();
8440	if (RT) {
8441	CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
8442	if (RAA == CGCXXABI::RAA_Indirect)
8443	return getIndirectByRef(Ty, FreeRegs > 0);
8444
8445	if (RAA == CGCXXABI::RAA_DirectInMemory)
8446	return getIndirectByValue(Ty);
8447	}
8448
8449	// Treat an enum type as its underlying type.
8450	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8451	Ty = EnumTy->getDecl()->getIntegerType();
8452
8453	auto SizeInRegs = llvm::alignTo(getContext().getTypeSize(Ty), 32) / 32;
8454
8455	if (isAggregateTypeForABI(Ty)) {
8456	// Structures with flexible arrays are always indirect.
8457	if (RT && RT->getDecl()->hasFlexibleArrayMember())
8458	return getIndirectByValue(Ty);
8459
8460	// Ignore empty structs/unions.
8461	if (isEmptyRecord(getContext(), Ty, true))
8462	return ABIArgInfo::getIgnore();
8463
8464	llvm::LLVMContext &LLVMContext = getVMContext();
8465
8466	llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
8467	SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
8468	llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
8469
8470	return FreeRegs >= SizeInRegs ?
8471	ABIArgInfo::getDirectInReg(Result) :
8472	ABIArgInfo::getDirect(Result, 0, nullptr, false);
8473	}
8474
8475	return Ty->isPromotableIntegerType() ?
8476	(FreeRegs >= SizeInRegs ? ABIArgInfo::getExtendInReg(Ty) :
8477	ABIArgInfo::getExtend(Ty)) :
8478	(FreeRegs >= SizeInRegs ? ABIArgInfo::getDirectInReg() :
8479	ABIArgInfo::getDirect());
8480	}
8481
8482	ABIArgInfo ARCABIInfo::classifyReturnType(QualType RetTy) const {
8483	if (RetTy->isAnyComplexType())
8484	return ABIArgInfo::getDirectInReg();
8485
8486	// Arguments of size > 4 registers are indirect.
8487	auto RetSize = llvm::alignTo(getContext().getTypeSize(RetTy), 32) / 32;
8488	if (RetSize > 4)
8489	return getIndirectByRef(RetTy, /HasFreeRegs/ true);
8490
8491	return DefaultABIInfo::classifyReturnType(RetTy);
8492	}
8493
8494	} // End anonymous namespace.
8495
8496	//===----------------------------------------------------------------------===//
8497	// XCore ABI Implementation
8498	//===----------------------------------------------------------------------===//
8499
8500	namespace {
8501
8502	/// A SmallStringEnc instance is used to build up the TypeString by passing
8503	/// it by reference between functions that append to it.
8504	typedef llvm::SmallString<128> SmallStringEnc;
8505
8506	/// TypeStringCache caches the meta encodings of Types.
8507	///
8508	/// The reason for caching TypeStrings is two fold:
8509	/// 1. To cache a type's encoding for later uses;
8510	/// 2. As a means to break recursive member type inclusion.
8511	///
8512	/// A cache Entry can have a Status of:
8513	/// NonRecursive: The type encoding is not recursive;
8514	/// Recursive: The type encoding is recursive;
8515	/// Incomplete: An incomplete TypeString;
8516	/// IncompleteUsed: An incomplete TypeString that has been used in a
8517	/// Recursive type encoding.
8518	///
8519	/// A NonRecursive entry will have all of its sub-members expanded as fully
8520	/// as possible. Whilst it may contain types which are recursive, the type
8521	/// itself is not recursive and thus its encoding may be safely used whenever
8522	/// the type is encountered.
8523	///
8524	/// A Recursive entry will have all of its sub-members expanded as fully as
8525	/// possible. The type itself is recursive and it may contain other types which
8526	/// are recursive. The Recursive encoding must not be used during the expansion
8527	/// of a recursive type's recursive branch. For simplicity the code uses
8528	/// IncompleteCount to reject all usage of Recursive encodings for member types.
8529	///
8530	/// An Incomplete entry is always a RecordType and only encodes its
8531	/// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
8532	/// are placed into the cache during type expansion as a means to identify and
8533	/// handle recursive inclusion of types as sub-members. If there is recursion
8534	/// the entry becomes IncompleteUsed.
8535	///
8536	/// During the expansion of a RecordType's members:
8537	///
8538	/// If the cache contains a NonRecursive encoding for the member type, the
8539	/// cached encoding is used;
8540	///
8541	/// If the cache contains a Recursive encoding for the member type, the
8542	/// cached encoding is 'Swapped' out, as it may be incorrect, and...
8543	///
8544	/// If the member is a RecordType, an Incomplete encoding is placed into the
8545	/// cache to break potential recursive inclusion of itself as a sub-member;
8546	///
8547	/// Once a member RecordType has been expanded, its temporary incomplete
8548	/// entry is removed from the cache. If a Recursive encoding was swapped out
8549	/// it is swapped back in;
8550	///
8551	/// If an incomplete entry is used to expand a sub-member, the incomplete
8552	/// entry is marked as IncompleteUsed. The cache keeps count of how many
8553	/// IncompleteUsed entries it currently contains in IncompleteUsedCount;
8554	///
8555	/// If a member's encoding is found to be a NonRecursive or Recursive viz:
8556	/// IncompleteUsedCount==0, the member's encoding is added to the cache.
8557	/// Else the member is part of a recursive type and thus the recursion has
8558	/// been exited too soon for the encoding to be correct for the member.
8559	///
8560	class TypeStringCache {
8561	enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
8562	struct Entry {
8563	std::string Str; // The encoded TypeString for the type.
8564	enum Status State; // Information about the encoding in 'Str'.
8565	std::string Swapped; // A temporary place holder for a Recursive encoding
8566	// during the expansion of RecordType's members.
8567	};
8568	std::map<const IdentifierInfo *, struct Entry> Map;
8569	unsigned IncompleteCount; // Number of Incomplete entries in the Map.
8570	unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
8571	public:
8572	TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
8573	void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
8574	bool removeIncomplete(const IdentifierInfo *ID);
8575	void addIfComplete(const IdentifierInfo *ID, StringRef Str,
8576	bool IsRecursive);
8577	StringRef lookupStr(const IdentifierInfo *ID);
8578	};
8579
8580	/// TypeString encodings for enum & union fields must be order.
8581	/// FieldEncoding is a helper for this ordering process.
8582	class FieldEncoding {
8583	bool HasName;
8584	std::string Enc;
8585	public:
8586	FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
8587	StringRef str() { return Enc; }
8588	bool operator<(const FieldEncoding &rhs) const {
8589	if (HasName != rhs.HasName) return HasName;
8590	return Enc < rhs.Enc;
8591	}
8592	};
8593
8594	class XCoreABIInfo : public DefaultABIInfo {
8595	public:
8596	XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8597	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8598	QualType Ty) const override;
8599	};
8600
8601	class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
8602	mutable TypeStringCache TSC;
8603	public:
8604	XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
8605	:TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
8606	void emitTargetMD(const Decl D, llvm::GlobalValue GV,
8607	CodeGen::CodeGenModule &M) const override;
8608	};
8609
8610	} // End anonymous namespace.
8611
8612	// TODO: this implementation is likely now redundant with the default
8613	// EmitVAArg.
8614	Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8615	QualType Ty) const {
8616	CGBuilderTy &Builder = CGF.Builder;
8617
8618	// Get the VAList.
8619	CharUnits SlotSize = CharUnits::fromQuantity(4);
8620	Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
8621
8622	// Handle the argument.
8623	ABIArgInfo AI = classifyArgumentType(Ty);
8624	CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
8625	llvm::Type *ArgTy = CGT.ConvertType(Ty);
8626	if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8627	AI.setCoerceToType(ArgTy);
8628	llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8629
8630	Address Val = Address::invalid();
8631	CharUnits ArgSize = CharUnits::Zero();
8632	switch (AI.getKind()) {
8633	case ABIArgInfo::Expand:
8634	case ABIArgInfo::CoerceAndExpand:
8635	case ABIArgInfo::InAlloca:
8636	llvm_unreachable("Unsupported ABI kind for va_arg");
8637	case ABIArgInfo::Ignore:
8638	Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
8639	ArgSize = CharUnits::Zero();
8640	break;
8641	case ABIArgInfo::Extend:
8642	case ABIArgInfo::Direct:
8643	Val = Builder.CreateBitCast(AP, ArgPtrTy);
8644	ArgSize = CharUnits::fromQuantity(
8645	getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
8646	ArgSize = ArgSize.alignTo(SlotSize);
8647	break;
8648	case ABIArgInfo::Indirect:
8649	Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
8650	Val = Address(Builder.CreateLoad(Val), TypeAlign);
8651	ArgSize = SlotSize;
8652	break;
8653	}
8654
8655	// Increment the VAList.
8656	if (!ArgSize.isZero()) {
8657	Address APN = Builder.CreateConstInBoundsByteGEP(AP, ArgSize);
8658	Builder.CreateStore(APN.getPointer(), VAListAddr);
8659	}
8660
8661	return Val;
8662	}
8663
8664	/// During the expansion of a RecordType, an incomplete TypeString is placed
8665	/// into the cache as a means to identify and break recursion.
8666	/// If there is a Recursive encoding in the cache, it is swapped out and will
8667	/// be reinserted by removeIncomplete().
8668	/// All other types of encoding should have been used rather than arriving here.
8669	void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
8670	std::string StubEnc) {
8671	if (!ID)
8672	return;
8673	Entry &E = Map[ID];
8674	(0) . __assert_fail ("(E.Str.empty() \|\| E.State == Recursive) && \"Incorrectly use of addIncomplete\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8675, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert( (E.Str.empty() \|\| E.State == Recursive) &&
8675	(0) . __assert_fail ("(E.Str.empty() \|\| E.State == Recursive) && \"Incorrectly use of addIncomplete\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8675, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Incorrectly use of addIncomplete");
8676	(0) . __assert_fail ("!StubEnc.empty() && \"Passing an empty string to addIncomplete()\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8676, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8677	E.Swapped.swap(E.Str); // swap out the Recursive
8678	E.Str.swap(StubEnc);
8679	E.State = Incomplete;
8680	++IncompleteCount;
8681	}
8682
8683	/// Once the RecordType has been expanded, the temporary incomplete TypeString
8684	/// must be removed from the cache.
8685	/// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8686	/// Returns true if the RecordType was defined recursively.
8687	bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8688	if (!ID)
8689	return false;
8690	auto I = Map.find(ID);
8691	(0) . __assert_fail ("I != Map.end() && \"Entry not present\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8691, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(I != Map.end() && "Entry not present");
8692	Entry &E = I->second;
8693	(0) . __assert_fail ("(E.State == Incomplete \|\| E.State == IncompleteUsed) && \"Entry must be an incomplete type\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8695, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert( (E.State == Incomplete \|\|
8694	(0) . __assert_fail ("(E.State == Incomplete \|\| E.State == IncompleteUsed) && \"Entry must be an incomplete type\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8695, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> E.State == IncompleteUsed) &&
8695	(0) . __assert_fail ("(E.State == Incomplete \|\| E.State == IncompleteUsed) && \"Entry must be an incomplete type\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8695, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "Entry must be an incomplete type");
8696	bool IsRecursive = false;
8697	if (E.State == IncompleteUsed) {
8698	// We made use of our Incomplete encoding, thus we are recursive.
8699	IsRecursive = true;
8700	--IncompleteUsedCount;
8701	}
8702	if (E.Swapped.empty())
8703	Map.erase(I);
8704	else {
8705	// Swap the Recursive back.
8706	E.Swapped.swap(E.Str);
8707	E.Swapped.clear();
8708	E.State = Recursive;
8709	}
8710	--IncompleteCount;
8711	return IsRecursive;
8712	}
8713
8714	/// Add the encoded TypeString to the cache only if it is NonRecursive or
8715	/// Recursive (viz: all sub-members were expanded as fully as possible).
8716	void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8717	bool IsRecursive) {
8718	if (!ID \|\| IncompleteUsedCount)
8719	return; // No key or it is is an incomplete sub-type so don't add.
8720	Entry &E = Map[ID];
8721	if (IsRecursive && !E.Str.empty()) {
8722	(0) . __assert_fail ("E.State==Recursive && E.Str.size() == Str.size() && \"This is not the same Recursive entry\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8723, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(E.State==Recursive && E.Str.size() == Str.size() &&
8723	(0) . __assert_fail ("E.State==Recursive && E.Str.size() == Str.size() && \"This is not the same Recursive entry\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8723, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true"> "This is not the same Recursive entry");
8724	// The parent container was not recursive after all, so we could have used
8725	// this Recursive sub-member entry after all, but we assumed the worse when
8726	// we started viz: IncompleteCount!=0.
8727	return;
8728	}
8729	(0) . __assert_fail ("E.Str.empty() && \"Entry already present\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 8729, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(E.Str.empty() && "Entry already present");
8730	E.Str = Str.str();
8731	E.State = IsRecursive? Recursive : NonRecursive;
8732	}
8733
8734	/// Return a cached TypeString encoding for the ID. If there isn't one, or we
8735	/// are recursively expanding a type (IncompleteCount != 0) and the cached
8736	/// encoding is Recursive, return an empty StringRef.
8737	StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8738	if (!ID)
8739	return StringRef(); // We have no key.
8740	auto I = Map.find(ID);
8741	if (I == Map.end())
8742	return StringRef(); // We have no encoding.
8743	Entry &E = I->second;
8744	if (E.State == Recursive && IncompleteCount)
8745	return StringRef(); // We don't use Recursive encodings for member types.
8746
8747	if (E.State == Incomplete) {
8748	// The incomplete type is being used to break out of recursion.
8749	E.State = IncompleteUsed;
8750	++IncompleteUsedCount;
8751	}
8752	return E.Str;
8753	}
8754
8755	/// The XCore ABI includes a type information section that communicates symbol
8756	/// type information to the linker. The linker uses this information to verify
8757	/// safety/correctness of things such as array bound and pointers et al.
8758	/// The ABI only requires C (and XC) language modules to emit TypeStrings.
8759	/// This type information (TypeString) is emitted into meta data for all global
8760	/// symbols: definitions, declarations, functions & variables.
8761	///
8762	/// The TypeString carries type, qualifier, name, size & value details.
8763	/// Please see 'Tools Development Guide' section 2.16.2 for format details:
8764	/// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8765	/// The output is tested by test/CodeGen/xcore-stringtype.c.
8766	///
8767	static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8768	CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8769
8770	/// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8771	void XCoreTargetCodeGenInfo::emitTargetMD(const Decl D, llvm::GlobalValue GV,
8772	CodeGen::CodeGenModule &CGM) const {
8773	SmallStringEnc Enc;
8774	if (getTypeString(Enc, D, CGM, TSC)) {
8775	llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8776	llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8777	llvm::MDString::get(Ctx, Enc.str())};
8778	llvm::NamedMDNode *MD =
8779	CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8780	MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8781	}
8782	}
8783
8784	//===----------------------------------------------------------------------===//
8785	// SPIR ABI Implementation
8786	//===----------------------------------------------------------------------===//
8787
8788	namespace {
8789	class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8790	public:
8791	SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8792	: TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8793	unsigned getOpenCLKernelCallingConv() const override;
8794	};
8795
8796	} // End anonymous namespace.
8797
8798	namespace clang {
8799	namespace CodeGen {
8800	void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) {
8801	DefaultABIInfo SPIRABI(CGM.getTypes());
8802	SPIRABI.computeInfo(FI);
8803	}
8804	}
8805	}
8806
8807	unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8808	return llvm::CallingConv::SPIR_KERNEL;
8809	}
8810
8811	static bool appendType(SmallStringEnc &Enc, QualType QType,
8812	const CodeGen::CodeGenModule &CGM,
8813	TypeStringCache &TSC);
8814
8815	/// Helper function for appendRecordType().
8816	/// Builds a SmallVector containing the encoded field types in declaration
8817	/// order.
8818	static bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE,
8819	const RecordDecl *RD,
8820	const CodeGen::CodeGenModule &CGM,
8821	TypeStringCache &TSC) {
8822	for (const auto *Field : RD->fields()) {
8823	SmallStringEnc Enc;
8824	Enc += "m(";
8825	Enc += Field->getName();
8826	Enc += "){";
8827	if (Field->isBitField()) {
8828	Enc += "b(";
8829	llvm::raw_svector_ostream OS(Enc);
8830	OS << Field->getBitWidthValue(CGM.getContext());
8831	Enc += ':';
8832	}
8833	if (!appendType(Enc, Field->getType(), CGM, TSC))
8834	return false;
8835	if (Field->isBitField())
8836	Enc += ')';
8837	Enc += '}';
8838	FE.emplace_back(!Field->getName().empty(), Enc);
8839	}
8840	return true;
8841	}
8842
8843	/// Appends structure and union types to Enc and adds encoding to cache.
8844	/// Recursively calls appendType (via extractFieldType) for each field.
8845	/// Union types have their fields ordered according to the ABI.
8846	static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8847	const CodeGen::CodeGenModule &CGM,
8848	TypeStringCache &TSC, const IdentifierInfo *ID) {
8849	// Append the cached TypeString if we have one.
8850	StringRef TypeString = TSC.lookupStr(ID);
8851	if (!TypeString.empty()) {
8852	Enc += TypeString;
8853	return true;
8854	}
8855
8856	// Start to emit an incomplete TypeString.
8857	size_t Start = Enc.size();
8858	Enc += (RT->isUnionType()? 'u' : 's');
8859	Enc += '(';
8860	if (ID)
8861	Enc += ID->getName();
8862	Enc += "){";
8863
8864	// We collect all encoded fields and order as necessary.
8865	bool IsRecursive = false;
8866	const RecordDecl *RD = RT->getDecl()->getDefinition();
8867	if (RD && !RD->field_empty()) {
8868	// An incomplete TypeString stub is placed in the cache for this RecordType
8869	// so that recursive calls to this RecordType will use it whilst building a
8870	// complete TypeString for this RecordType.
8871	SmallVector<FieldEncoding, 16> FE;
8872	std::string StubEnc(Enc.substr(Start).str());
8873	StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8874	TSC.addIncomplete(ID, std::move(StubEnc));
8875	if (!extractFieldType(FE, RD, CGM, TSC)) {
8876	(void) TSC.removeIncomplete(ID);
8877	return false;
8878	}
8879	IsRecursive = TSC.removeIncomplete(ID);
8880	// The ABI requires unions to be sorted but not structures.
8881	// See FieldEncoding::operator< for sort algorithm.
8882	if (RT->isUnionType())
8883	llvm::sort(FE);
8884	// We can now complete the TypeString.
8885	unsigned E = FE.size();
8886	for (unsigned I = 0; I != E; ++I) {
8887	if (I)
8888	Enc += ',';
8889	Enc += FE[I].str();
8890	}
8891	}
8892	Enc += '}';
8893	TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8894	return true;
8895	}
8896
8897	/// Appends enum types to Enc and adds the encoding to the cache.
8898	static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8899	TypeStringCache &TSC,
8900	const IdentifierInfo *ID) {
8901	// Append the cached TypeString if we have one.
8902	StringRef TypeString = TSC.lookupStr(ID);
8903	if (!TypeString.empty()) {
8904	Enc += TypeString;
8905	return true;
8906	}
8907
8908	size_t Start = Enc.size();
8909	Enc += "e(";
8910	if (ID)
8911	Enc += ID->getName();
8912	Enc += "){";
8913
8914	// We collect all encoded enumerations and order them alphanumerically.
8915	if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8916	SmallVector<FieldEncoding, 16> FE;
8917	for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8918	++I) {
8919	SmallStringEnc EnumEnc;
8920	EnumEnc += "m(";
8921	EnumEnc += I->getName();
8922	EnumEnc += "){";
8923	I->getInitVal().toString(EnumEnc);
8924	EnumEnc += '}';
8925	FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8926	}
8927	llvm::sort(FE);
8928	unsigned E = FE.size();
8929	for (unsigned I = 0; I != E; ++I) {
8930	if (I)
8931	Enc += ',';
8932	Enc += FE[I].str();
8933	}
8934	}
8935	Enc += '}';
8936	TSC.addIfComplete(ID, Enc.substr(Start), false);
8937	return true;
8938	}
8939
8940	/// Appends type's qualifier to Enc.
8941	/// This is done prior to appending the type's encoding.
8942	static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8943	// Qualifiers are emitted in alphabetical order.
8944	static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8945	int Lookup = 0;
8946	if (QT.isConstQualified())
8947	Lookup += 1<<0;
8948	if (QT.isRestrictQualified())
8949	Lookup += 1<<1;
8950	if (QT.isVolatileQualified())
8951	Lookup += 1<<2;
8952	Enc += Table[Lookup];
8953	}
8954
8955	/// Appends built-in types to Enc.
8956	static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8957	const char *EncType;
8958	switch (BT->getKind()) {
8959	case BuiltinType::Void:
8960	EncType = "0";
8961	break;
8962	case BuiltinType::Bool:
8963	EncType = "b";
8964	break;
8965	case BuiltinType::Char_U:
8966	EncType = "uc";
8967	break;
8968	case BuiltinType::UChar:
8969	EncType = "uc";
8970	break;
8971	case BuiltinType::SChar:
8972	EncType = "sc";
8973	break;
8974	case BuiltinType::UShort:
8975	EncType = "us";
8976	break;
8977	case BuiltinType::Short:
8978	EncType = "ss";
8979	break;
8980	case BuiltinType::UInt:
8981	EncType = "ui";
8982	break;
8983	case BuiltinType::Int:
8984	EncType = "si";
8985	break;
8986	case BuiltinType::ULong:
8987	EncType = "ul";
8988	break;
8989	case BuiltinType::Long:
8990	EncType = "sl";
8991	break;
8992	case BuiltinType::ULongLong:
8993	EncType = "ull";
8994	break;
8995	case BuiltinType::LongLong:
8996	EncType = "sll";
8997	break;
8998	case BuiltinType::Float:
8999	EncType = "ft";
9000	break;
9001	case BuiltinType::Double:
9002	EncType = "d";
9003	break;
9004	case BuiltinType::LongDouble:
9005	EncType = "ld";
9006	break;
9007	default:
9008	return false;
9009	}
9010	Enc += EncType;
9011	return true;
9012	}
9013
9014	/// Appends a pointer encoding to Enc before calling appendType for the pointee.
9015	static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
9016	const CodeGen::CodeGenModule &CGM,
9017	TypeStringCache &TSC) {
9018	Enc += "p(";
9019	if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
9020	return false;
9021	Enc += ')';
9022	return true;
9023	}
9024
9025	/// Appends array encoding to Enc before calling appendType for the element.
9026	static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
9027	const ArrayType *AT,
9028	const CodeGen::CodeGenModule &CGM,
9029	TypeStringCache &TSC, StringRef NoSizeEnc) {
9030	if (AT->getSizeModifier() != ArrayType::Normal)
9031	return false;
9032	Enc += "a(";
9033	if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
9034	CAT->getSize().toStringUnsigned(Enc);
9035	else
9036	Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
9037	Enc += ':';
9038	// The Qualifiers should be attached to the type rather than the array.
9039	appendQualifier(Enc, QT);
9040	if (!appendType(Enc, AT->getElementType(), CGM, TSC))
9041	return false;
9042	Enc += ')';
9043	return true;
9044	}
9045
9046	/// Appends a function encoding to Enc, calling appendType for the return type
9047	/// and the arguments.
9048	static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
9049	const CodeGen::CodeGenModule &CGM,
9050	TypeStringCache &TSC) {
9051	Enc += "f{";
9052	if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
9053	return false;
9054	Enc += "}(";
9055	if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
9056	// N.B. we are only interested in the adjusted param types.
9057	auto I = FPT->param_type_begin();
9058	auto E = FPT->param_type_end();
9059	if (I != E) {
9060	do {
9061	if (!appendType(Enc, *I, CGM, TSC))
9062	return false;
9063	++I;
9064	if (I != E)
9065	Enc += ',';
9066	} while (I != E);
9067	if (FPT->isVariadic())
9068	Enc += ",va";
9069	} else {
9070	if (FPT->isVariadic())
9071	Enc += "va";
9072	else
9073	Enc += '0';
9074	}
9075	}
9076	Enc += ')';
9077	return true;
9078	}
9079
9080	/// Handles the type's qualifier before dispatching a call to handle specific
9081	/// type encodings.
9082	static bool appendType(SmallStringEnc &Enc, QualType QType,
9083	const CodeGen::CodeGenModule &CGM,
9084	TypeStringCache &TSC) {
9085
9086	QualType QT = QType.getCanonicalType();
9087
9088	if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
9089	// The Qualifiers should be attached to the type rather than the array.
9090	// Thus we don't call appendQualifier() here.
9091	return appendArrayType(Enc, QT, AT, CGM, TSC, "");
9092
9093	appendQualifier(Enc, QT);
9094
9095	if (const BuiltinType *BT = QT->getAs<BuiltinType>())
9096	return appendBuiltinType(Enc, BT);
9097
9098	if (const PointerType *PT = QT->getAs<PointerType>())
9099	return appendPointerType(Enc, PT, CGM, TSC);
9100
9101	if (const EnumType *ET = QT->getAs<EnumType>())
9102	return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
9103
9104	if (const RecordType *RT = QT->getAsStructureType())
9105	return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
9106
9107	if (const RecordType *RT = QT->getAsUnionType())
9108	return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
9109
9110	if (const FunctionType *FT = QT->getAs<FunctionType>())
9111	return appendFunctionType(Enc, FT, CGM, TSC);
9112
9113	return false;
9114	}
9115
9116	static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
9117	CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
9118	if (!D)
9119	return false;
9120
9121	if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
9122	if (FD->getLanguageLinkage() != CLanguageLinkage)
9123	return false;
9124	return appendType(Enc, FD->getType(), CGM, TSC);
9125	}
9126
9127	if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
9128	if (VD->getLanguageLinkage() != CLanguageLinkage)
9129	return false;
9130	QualType QT = VD->getType().getCanonicalType();
9131	if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
9132	// Global ArrayTypes are given a size of '*' if the size is unknown.
9133	// The Qualifiers should be attached to the type rather than the array.
9134	// Thus we don't call appendQualifier() here.
9135	return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
9136	}
9137	return appendType(Enc, QT, CGM, TSC);
9138	}
9139	return false;
9140	}
9141
9142	//===----------------------------------------------------------------------===//
9143	// RISCV ABI Implementation
9144	//===----------------------------------------------------------------------===//
9145
9146	namespace {
9147	class RISCVABIInfo : public DefaultABIInfo {
9148	private:
9149	unsigned XLen; // Size of the integer ('x') registers in bits.
9150	static const int NumArgGPRs = 8;
9151
9152	public:
9153	RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
9154	: DefaultABIInfo(CGT), XLen(XLen) {}
9155
9156	// DefaultABIInfo's classifyReturnType and classifyArgumentType are
9157	// non-virtual, but computeInfo is virtual, so we overload it.
9158	void computeInfo(CGFunctionInfo &FI) const override;
9159
9160	ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed,
9161	int &ArgGPRsLeft) const;
9162	ABIArgInfo classifyReturnType(QualType RetTy) const;
9163
9164	Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
9165	QualType Ty) const override;
9166
9167	ABIArgInfo extendType(QualType Ty) const;
9168	};
9169	} // end anonymous namespace
9170
9171	void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
9172	QualType RetTy = FI.getReturnType();
9173	if (!getCXXABI().classifyReturnType(FI))
9174	FI.getReturnInfo() = classifyReturnType(RetTy);
9175
9176	// IsRetIndirect is true if classifyArgumentType indicated the value should
9177	// be passed indirect or if the type size is greater than 2*xlen. e.g. fp128
9178	// is passed direct in LLVM IR, relying on the backend lowering code to
9179	// rewrite the argument list and pass indirectly on RV32.
9180	bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect \|\|
9181	getContext().getTypeSize(RetTy) > (2 * XLen);
9182
9183	// We must track the number of GPRs used in order to conform to the RISC-V
9184	// ABI, as integer scalars passed in registers should have signext/zeroext
9185	// when promoted, but are anyext if passed on the stack. As GPR usage is
9186	// different for variadic arguments, we must also track whether we are
9187	// examining a vararg or not.
9188	int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
9189	int NumFixedArgs = FI.getNumRequiredArgs();
9190
9191	int ArgNum = 0;
9192	for (auto &ArgInfo : FI.arguments()) {
9193	bool IsFixed = ArgNum < NumFixedArgs;
9194	ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft);
9195	ArgNum++;
9196	}
9197	}
9198
9199	ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
9200	int &ArgGPRsLeft) const {
9201	(0) . __assert_fail ("ArgGPRsLeft <= NumArgGPRs && \"Arg GPR tracking underflow\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 9201, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
9202	Ty = useFirstFieldIfTransparentUnion(Ty);
9203
9204	// Structures with either a non-trivial destructor or a non-trivial
9205	// copy constructor are always passed indirectly.
9206	if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
9207	if (ArgGPRsLeft)
9208	ArgGPRsLeft -= 1;
9209	return getNaturalAlignIndirect(Ty, /ByVal=/RAA ==
9210	CGCXXABI::RAA_DirectInMemory);
9211	}
9212
9213	// Ignore empty structs/unions.
9214	if (isEmptyRecord(getContext(), Ty, true))
9215	return ABIArgInfo::getIgnore();
9216
9217	uint64_t Size = getContext().getTypeSize(Ty);
9218	uint64_t NeededAlign = getContext().getTypeAlign(Ty);
9219	bool MustUseStack = false;
9220	// Determine the number of GPRs needed to pass the current argument
9221	// according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
9222	// register pairs, so may consume 3 registers.
9223	int NeededArgGPRs = 1;
9224	if (!IsFixed && NeededAlign == 2 * XLen)
9225	NeededArgGPRs = 2 + (ArgGPRsLeft % 2);
9226	else if (Size > XLen && Size <= 2 * XLen)
9227	NeededArgGPRs = 2;
9228
9229	if (NeededArgGPRs > ArgGPRsLeft) {
9230	MustUseStack = true;
9231	NeededArgGPRs = ArgGPRsLeft;
9232	}
9233
9234	ArgGPRsLeft -= NeededArgGPRs;
9235
9236	if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) {
9237	// Treat an enum type as its underlying type.
9238	if (const EnumType *EnumTy = Ty->getAs<EnumType>())
9239	Ty = EnumTy->getDecl()->getIntegerType();
9240
9241	// All integral types are promoted to XLen width, unless passed on the
9242	// stack.
9243	if (Size < XLen && Ty->isIntegralOrEnumerationType() && !MustUseStack) {
9244	return extendType(Ty);
9245	}
9246
9247	return ABIArgInfo::getDirect();
9248	}
9249
9250	// Aggregates which are <= 2*XLen will be passed in registers if possible,
9251	// so coerce to integers.
9252	if (Size <= 2 * XLen) {
9253	unsigned Alignment = getContext().getTypeAlign(Ty);
9254
9255	// Use a single XLen int if possible, 2XLen if 2XLen alignment is
9256	// required, and a 2-element XLen array if only XLen alignment is required.
9257	if (Size <= XLen) {
9258	return ABIArgInfo::getDirect(
9259	llvm::IntegerType::get(getVMContext(), XLen));
9260	} else if (Alignment == 2 * XLen) {
9261	return ABIArgInfo::getDirect(
9262	llvm::IntegerType::get(getVMContext(), 2 * XLen));
9263	} else {
9264	return ABIArgInfo::getDirect(llvm::ArrayType::get(
9265	llvm::IntegerType::get(getVMContext(), XLen), 2));
9266	}
9267	}
9268	return getNaturalAlignIndirect(Ty, /ByVal=/false);
9269	}
9270
9271	ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy) const {
9272	if (RetTy->isVoidType())
9273	return ABIArgInfo::getIgnore();
9274
9275	int ArgGPRsLeft = 2;
9276
9277	// The rules for return and argument types are the same, so defer to
9278	// classifyArgumentType.
9279	return classifyArgumentType(RetTy, /IsFixed=/true, ArgGPRsLeft);
9280	}
9281
9282	Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
9283	QualType Ty) const {
9284	CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8);
9285
9286	// Empty records are ignored for parameter passing purposes.
9287	if (isEmptyRecord(getContext(), Ty, true)) {
9288	Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
9289	Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
9290	return Addr;
9291	}
9292
9293	std::pair<CharUnits, CharUnits> SizeAndAlign =
9294	getContext().getTypeInfoInChars(Ty);
9295
9296	// Arguments bigger than 2*Xlen bytes are passed indirectly.
9297	bool IsIndirect = SizeAndAlign.first > 2 * SlotSize;
9298
9299	return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, SizeAndAlign,
9300	SlotSize, /AllowHigherAlign=/true);
9301	}
9302
9303	ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
9304	int TySize = getContext().getTypeSize(Ty);
9305	// RV64 ABI requires unsigned 32 bit integers to be sign extended.
9306	if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
9307	return ABIArgInfo::getSignExtend(Ty);
9308	return ABIArgInfo::getExtend(Ty);
9309	}
9310
9311	namespace {
9312	class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
9313	public:
9314	RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
9315	: TargetCodeGenInfo(new RISCVABIInfo(CGT, XLen)) {}
9316
9317	void setTargetAttributes(const Decl D, llvm::GlobalValue GV,
9318	CodeGen::CodeGenModule &CGM) const override {
9319	const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
9320	if (!FD) return;
9321
9322	const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
9323	if (!Attr)
9324	return;
9325
9326	const char *Kind;
9327	switch (Attr->getInterrupt()) {
9328	case RISCVInterruptAttr::user: Kind = "user"; break;
9329	case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break;
9330	case RISCVInterruptAttr::machine: Kind = "machine"; break;
9331	}
9332
9333	auto *Fn = cast<llvm::Function>(GV);
9334
9335	Fn->addFnAttr("interrupt", Kind);
9336	}
9337	};
9338	} // namespace
9339
9340	//===----------------------------------------------------------------------===//
9341	// Driver code
9342	//===----------------------------------------------------------------------===//
9343
9344	bool CodeGenModule::supportsCOMDAT() const {
9345	return getTriple().supportsCOMDAT();
9346	}
9347
9348	const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
9349	if (TheTargetCodeGenInfo)
9350	return *TheTargetCodeGenInfo;
9351
9352	// Helper to set the unique_ptr while still keeping the return value.
9353	auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
9354	this->TheTargetCodeGenInfo.reset(P);
9355	return *P;
9356	};
9357
9358	const llvm::Triple &Triple = getTarget().getTriple();
9359	switch (Triple.getArch()) {
9360	default:
9361	return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
9362
9363	case llvm::Triple::le32:
9364	return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9365	case llvm::Triple::mips:
9366	case llvm::Triple::mipsel:
9367	if (Triple.getOS() == llvm::Triple::NaCl)
9368	return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9369	return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
9370
9371	case llvm::Triple::mips64:
9372	case llvm::Triple::mips64el:
9373	return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
9374
9375	case llvm::Triple::avr:
9376	return SetCGInfo(new AVRTargetCodeGenInfo(Types));
9377
9378	case llvm::Triple::aarch64:
9379	case llvm::Triple::aarch64_be: {
9380	AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
9381	if (getTarget().getABI() == "darwinpcs")
9382	Kind = AArch64ABIInfo::DarwinPCS;
9383	else if (Triple.isOSWindows())
9384	return SetCGInfo(
9385	new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64));
9386
9387	return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
9388	}
9389
9390	case llvm::Triple::wasm32:
9391	case llvm::Triple::wasm64:
9392	return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
9393
9394	case llvm::Triple::arm:
9395	case llvm::Triple::armeb:
9396	case llvm::Triple::thumb:
9397	case llvm::Triple::thumbeb: {
9398	if (Triple.getOS() == llvm::Triple::Win32) {
9399	return SetCGInfo(
9400	new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
9401	}
9402
9403	ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
9404	StringRef ABIStr = getTarget().getABI();
9405	if (ABIStr == "apcs-gnu")
9406	Kind = ARMABIInfo::APCS;
9407	else if (ABIStr == "aapcs16")
9408	Kind = ARMABIInfo::AAPCS16_VFP;
9409	else if (CodeGenOpts.FloatABI == "hard" \|\|
9410	(CodeGenOpts.FloatABI != "soft" &&
9411	(Triple.getEnvironment() == llvm::Triple::GNUEABIHF \|\|
9412	Triple.getEnvironment() == llvm::Triple::MuslEABIHF \|\|
9413	Triple.getEnvironment() == llvm::Triple::EABIHF)))
9414	Kind = ARMABIInfo::AAPCS_VFP;
9415
9416	return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
9417	}
9418
9419	case llvm::Triple::ppc:
9420	return SetCGInfo(
9421	new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
9422	case llvm::Triple::ppc64:
9423	if (Triple.isOSBinFormatELF()) {
9424	PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
9425	if (getTarget().getABI() == "elfv2")
9426	Kind = PPC64_SVR4_ABIInfo::ELFv2;
9427	bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9428	bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9429
9430	return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9431	IsSoftFloat));
9432	} else
9433	return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
9434	case llvm::Triple::ppc64le: {
9435	(0) . __assert_fail ("Triple.isOSBinFormatELF() && \"PPC64 LE non-ELF not supported!\"", "/home/seafit/code_projects/clang_source/clang/lib/CodeGen/TargetInfo.cpp", 9435, __PRETTY_FUNCTION__))" file_link="../../../include/assert.h.html#88" macro="true">assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
9436	PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
9437	if (getTarget().getABI() == "elfv1" \|\| getTarget().getABI() == "elfv1-qpx")
9438	Kind = PPC64_SVR4_ABIInfo::ELFv1;
9439	bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9440	bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9441
9442	return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9443	IsSoftFloat));
9444	}
9445
9446	case llvm::Triple::nvptx:
9447	case llvm::Triple::nvptx64:
9448	return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
9449
9450	case llvm::Triple::msp430:
9451	return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
9452
9453	case llvm::Triple::riscv32:
9454	return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 32));
9455	case llvm::Triple::riscv64:
9456	return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 64));
9457
9458	case llvm::Triple::systemz: {
9459	bool HasVector = getTarget().getABI() == "vector";
9460	return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
9461	}
9462
9463	case llvm::Triple::tce:
9464	case llvm::Triple::tcele:
9465	return SetCGInfo(new TCETargetCodeGenInfo(Types));
9466
9467	case llvm::Triple::x86: {
9468	bool IsDarwinVectorABI = Triple.isOSDarwin();
9469	bool RetSmallStructInRegABI =
9470	X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
9471	bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
9472
9473	if (Triple.getOS() == llvm::Triple::Win32) {
9474	return SetCGInfo(new WinX86_32TargetCodeGenInfo(
9475	Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9476	IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
9477	} else {
9478	return SetCGInfo(new X86_32TargetCodeGenInfo(
9479	Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9480	IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
9481	CodeGenOpts.FloatABI == "soft"));
9482	}
9483	}
9484
9485	case llvm::Triple::x86_64: {
9486	StringRef ABI = getTarget().getABI();
9487	X86AVXABILevel AVXLevel =
9488	(ABI == "avx512"
9489	? X86AVXABILevel::AVX512
9490	: ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
9491
9492	switch (Triple.getOS()) {
9493	case llvm::Triple::Win32:
9494	return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
9495	case llvm::Triple::PS4:
9496	return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
9497	default:
9498	return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
9499	}
9500	}
9501	case llvm::Triple::hexagon:
9502	return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
9503	case llvm::Triple::lanai:
9504	return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
9505	case llvm::Triple::r600:
9506	return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9507	case llvm::Triple::amdgcn:
9508	return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9509	case llvm::Triple::sparc:
9510	return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
9511	case llvm::Triple::sparcv9:
9512	return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
9513	case llvm::Triple::xcore:
9514	return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
9515	case llvm::Triple::arc:
9516	return SetCGInfo(new ARCTargetCodeGenInfo(Types));
9517	case llvm::Triple::spir:
9518	case llvm::Triple::spir64:
9519	return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
9520	}
9521	}
9522
9523	/// Create an OpenCL kernel for an enqueued block.
9524	///
9525	/// The kernel has the same function type as the block invoke function. Its
9526	/// name is the name of the block invoke function postfixed with "_kernel".
9527	/// It simply calls the block invoke function then returns.
9528	llvm::Function *
9529	TargetCodeGenInfo::createEnqueuedBlockKernel(CodeGenFunction &CGF,
9530	llvm::Function *Invoke,
9531	llvm::Value *BlockLiteral) const {
9532	auto *InvokeFT = Invoke->getFunctionType();
9533	llvm::SmallVector<llvm::Type *, 2> ArgTys;
9534	for (auto &P : InvokeFT->params())
9535	ArgTys.push_back(P);
9536	auto &C = CGF.getLLVMContext();
9537	std::string Name = Invoke->getName().str() + "_kernel";
9538	auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9539	auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
9540	&CGF.CGM.getModule());
9541	auto IP = CGF.Builder.saveIP();
9542	auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9543	auto &Builder = CGF.Builder;
9544	Builder.SetInsertPoint(BB);
9545	llvm::SmallVector<llvm::Value *, 2> Args;
9546	for (auto &A : F->args())
9547	Args.push_back(&A);
9548	Builder.CreateCall(Invoke, Args);
9549	Builder.CreateRetVoid();
9550	Builder.restoreIP(IP);
9551	return F;
9552	}
9553
9554	/// Create an OpenCL kernel for an enqueued block.
9555	///
9556	/// The type of the first argument (the block literal) is the struct type
9557	/// of the block literal instead of a pointer type. The first argument
9558	/// (block literal) is passed directly by value to the kernel. The kernel
9559	/// allocates the same type of struct on stack and stores the block literal
9560	/// to it and passes its pointer to the block invoke function. The kernel
9561	/// has "enqueued-block" function attribute and kernel argument metadata.
9562	llvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
9563	CodeGenFunction &CGF, llvm::Function *Invoke,
9564	llvm::Value *BlockLiteral) const {
9565	auto &Builder = CGF.Builder;
9566	auto &C = CGF.getLLVMContext();
9567
9568	auto *BlockTy = BlockLiteral->getType()->getPointerElementType();
9569	auto *InvokeFT = Invoke->getFunctionType();
9570	llvm::SmallVector<llvm::Type *, 2> ArgTys;
9571	llvm::SmallVector<llvm::Metadata *, 8> AddressQuals;
9572	llvm::SmallVector<llvm::Metadata *, 8> AccessQuals;
9573	llvm::SmallVector<llvm::Metadata *, 8> ArgTypeNames;
9574	llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
9575	llvm::SmallVector<llvm::Metadata *, 8> ArgTypeQuals;
9576	llvm::SmallVector<llvm::Metadata *, 8> ArgNames;
9577
9578	ArgTys.push_back(BlockTy);
9579	ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9580	AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0)));
9581	ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9582	ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9583	AccessQuals.push_back(llvm::MDString::get(C, "none"));
9584	ArgNames.push_back(llvm::MDString::get(C, "block_literal"));
9585	for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
9586	ArgTys.push_back(InvokeFT->getParamType(I));
9587	ArgTypeNames.push_back(llvm::MDString::get(C, "void*"));
9588	AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3)));
9589	AccessQuals.push_back(llvm::MDString::get(C, "none"));
9590	ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*"));
9591	ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9592	ArgNames.push_back(
9593	llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str()));
9594	}
9595	std::string Name = Invoke->getName().str() + "_kernel";
9596	auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9597	auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
9598	&CGF.CGM.getModule());
9599	F->addFnAttr("enqueued-block");
9600	auto IP = CGF.Builder.saveIP();
9601	auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9602	Builder.SetInsertPoint(BB);
9603	unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy);
9604	auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr);
9605	BlockPtr->setAlignment(BlockAlign);
9606	Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign);
9607	auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0));
9608	llvm::SmallVector<llvm::Value *, 2> Args;
9609	Args.push_back(Cast);
9610	for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I)
9611	Args.push_back(I);
9612	Builder.CreateCall(Invoke, Args);
9613	Builder.CreateRetVoid();
9614	Builder.restoreIP(IP);
9615
9616	F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals));
9617	F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals));
9618	F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames));
9619	F->setMetadata("kernel_arg_base_type",
9620	llvm::MDNode::get(C, ArgBaseTypeNames));
9621	F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals));
9622	if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
9623	F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames));
9624
9625	return F;
9626	}
9627